Search Result

2024

				[KrSc24] F. Krebs and K. Schneider Memory Footprint Reduction for Dataflow Process Networks using Virtual Channels Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[WeSc24a] M.C. Werner and K. Schneider From Imperative Sequential Structured Text Models to Synchronous Quartz and Sequentially Constructive Models Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[WeSc24b] M.C. Werner and K. Schneider PLCreX -- Open-Source Project for Simplification, Transformation, Analysis, and Validation of Programmable Logic Controllers Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)

2023

				[BhKS23] A. Bhagyanath and N. Kercher and K. Schneider Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann Architectures Formal Methods and Models for Codesign (MEMOCODE)
				[BhSc23] A. Bhagyanath and K. Schneider Program Balancing in Compilation for Buffered Hybrid Dataflow Processors Computer Architectures and Platforms at Computer Software and Applications Conference (CAP@COMPSAC)
				[RoBS23] J. Roob and A. Bhagyanath and K. Schneider Towards Buffers as a Scalable Alternative to Registers for Processor-Local Memory Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[ScBh23] K. Schneider and A. Bhagyanath Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann Architectures Transactions on Embedded Computing Systems (TECS)
				[ThSc23] D. Theis and K. Schneider Towards a Basis for Endochronous Functions in Dataflow Process Networks Formal Methods and Models for Codesign (MEMOCODE)
				[WeRS23] L. Werner and J. Roob and K. Schneider Network-On-Chip Performance Evaluation by Synchronous Circuit Simulation Network on Chip Architectures (NoCArc)
				[WeSc23] M.C. Werner and K. Schneider Formal Methods-based Optimization of Dataflow Models with Translation to Synchronous Models Forum on Specification and Design Languages (FDL)

2022

				[BhSc22] A. Bhagyanath and K. Schneider Buffer Allocation for Exposed Datapath Architectures International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
				[RaSc22] O. Rafique and K. Schneider Data-aware Global Scheduling of Dataflow Process Networks Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[RaSc22b] O. Rafique and K. Schneider Synthesis of Parallel Software from Heterogeneous Dataflow Models Springer Nature Computer Science (SNCS)
				[ScBR22] K. Schneider and A. Bhagyanath and J. Roob Virtual Buffers for Exposed Datapath Architectures Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[ScBR22b] K. Schneider and A. Bhagyanath and J. Roob Code Generation Criteria for Buffered Exposed Datapath Architectures from Dataflow Graphs Languages, Compilers, and Tools for Embedded Systems (LCTES)
				[WeSc22] M.C. Werner and K. Schneider From IEC 61131-3 Function Block Diagrams to Sequentially Constructive Statecharts Forum on Specification and Design Languages (FDL)

2021

				[BaRS21] Y. Bai and O. Rafique and K. Schneider A Model-based Design Flow for Asynchronous Implementations from Synchronous Specifications Design, Automation and Test in Europe (DATE)
				[RBSY21] O. Rafique and Y. Bai and K. Schneider and G. Yan Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO Patterns Euromicro Conference on Digital System Design (DSD)
				[RBSY21a] O. Rafique and Y. Bai and K. Schneider and G. Yan Synthesis of Heterogeneous Dataflow Models from Synchronous Specifications Computers, Software, and Applications Conference (COMPSAC)
				[RaBS21] O. Rafique and Y. Bai and K. Schneider Case Study: Smart Building Automation System -- (Detailed Evaluation Report) Technical Report
				[RaSc21] O. Rafique and K. Schneider Integrating Kahn Process Networks as a Model of Computation in an Extendable Model-based Design Framework International Conference on Model Driven Engineering and Software Development (MODELSWARD)
				[Schn21a] K. Schneider Translating Structured Sequential Programs to Dataflow Graphs Formal Methods and Models for Codesign (MEMOCODE)
				[WeSc21] M. Werner and K. Schneider Translation of Continuous Function Charts to Imperative Synchronous Quartz Programs Formal Methods and Models for Codesign (MEMOCODE)

2020

				[DaSc20] M. Dahlem and K. Schneider Compiling synchronous languages to optimal move code for exposed datapath architectures International Workshop on Software and Compilers for Embedded Systems (SCOPES)
				[FGBK20] J. Froemmer and Y. Gowayed and N. Bannow and W. Kunz and C. Grimm and K. Schneider Area Estimation Framework for Digital Hardware Design Using Machine Learning Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[KoHS20] M. Köhler and F. Hasselwander and K. Schneider Properties of Invariants and Induction Lemmata Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[RaSc20] O. Rafique and K. Schneider Employing OpenCL as a Standard Hardware Abstraction in a Distributed Embedded System: A Case Study Conference on Cyber-Physical Systems and Internet-of-Things
				[RaSc20b] O. Rafique and K. Schneider SHeD: A Framework for Automatic Software Synthesis of Heterogeneous Dataflow Process Networks Euromicro Conference on Digital System Design (DSD)
				[WeSc20] M.C. Werner and K. Schneider Reengineering Programmable Logic Controllers Using Synchronous Programming Languages Forum on Specification and Design Languages (FDL)

2019

				[AnSc19] M. Anders and K. Schneider A Formal Semantics of Exposed Datapath Architectures with Buffered Processing Units Application of Concurrency to System Design (ACSD)
				[DeST19] P. Derler and K. Schneider and J.-P. Talpin Guest Editorial: Special Issue of ACM TECS on the ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017) ACM Transactions on Embedded Computing Systems (TECS)
				[FBAG19] J. Frömmer and N. Bannow and A. Aue and C. Grimm and K. Schneider Model-Based Configuration of a Coarse-Grained Reconfigurable Architecture Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[FBAG19a] J. Froemmer and N. Bannow and A. Aue and C. Grimm and K. Schneider Flexible Data Flow Architecture for Embedded Hardware Accelerators International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP)
				[KoSc19] M. Köhler and K. Schneider Inductive Proof Rules Beyond Safety Properties Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[RaKS19] O. Rafique and F. Krebs and K. Schneider Generating Efficient Parallel Code from the RVC-CAL Dataflow Language Euromicro Conference on Digital System Design (DSD)
				[RaSc19] O. Rafique and K. Schneider Evaluating OpenCL as a Standard Hardware Abstraction for a Model-based Synthesis Framework: A Case Study International Conference on Model Driven Engineering and Software Development (MODELSWARD)
				[RaSc19a] O. Rafique and K. Schneider Automatic Software Synthesis of Static and Dynamic Dataflow Process Networks International Workshop on Interplay of Model-Driven and Component-Based Software Engineering (ModComp)

2018

				[AnBS18] M. Anders and A. Bhagyanath and K. Schneider On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units Application of Concurrency to System Design (ACSD)
				[DaBS18] M. Dahlem and A. Bhagyanath and K. Schneider Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP Technical Report
				[DaBS18b] M. Dahlem and A. Bhagyanath and K. Schneider Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP Theory and Practice of Logic Programming (TPLP)
				[JaSc18] T. Jain and K. Schneider The Half Cleaner Lemma: Constructing Efficient Interconnection Networks from Sorting Networks Parallel Processing Letters
				[JaSc18a] T. Jain and K. Schneider Routing Partial Permutations in General Interconnection Networks based on Radix Sorting Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[JaSc18c] T. Jain and K. Schneider Routing Partial Permutations in Interconnection Networks based on Radix Sorting International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
				[JaSc18e] T. Jain and K. Schneider A Recursive Concentrator Circuit and its Application as a Building Block of an Interconnection Network
				[JaSc18f] T. Jain and K. Schneider Optimal Self-Routing Split Modules for Radix-based Interconnection Networks Formal Methods and Models for Codesign (MEMOCODE)
				[RaSc18] O. Rafique and K. Schneider A Model-based Synthesis Framework for the Execution of Dynamic Dataflow Actors International Conference on Internet of Things Embedded Systems and Communications (IINTEC)
				[ScDa18] K. Schneider and M. Dahlem Are Synchronous Programs Logic Programs?
				[SeSc18] M. Senftleben and K. Schneider Operational Characterization of Weak Memory Consistency Models International Conference on Architecture of Computing Systems (ARCS)
				[SeSc18a] M. Senftleben and K. Schneider Using Temporal Logics for Specifying Weak Memory Consistency Models International Journal of Critical Computer-Based Systems (IJCCBS)

2017

				[BhSc17] A. Bhagyanath and K. Schneider Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units Application of Concurrency to System Design (ACSD)
				[BhSc17a] A. Bhagyanath and K. Schneider Exploring different execution paradigms in exposed datapath architectures with buffered processing units International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
				[DJSG17] M. Dahlem and T. Jain and K. Schneider and M. Gillmann Automatic Synthesis of Optimal-Size Concentrators by Answer Set Programming Logic Programming and Nonmonotonic Reasoning (LPNMR)
				[JaSJ17] T. Jain and K. Schneider and A. Jain An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip Network on Chip Architectures (NoCArc)
				[JaSJ17b] T. Jain and K. Schneider and A. Jain Deriving Concentrators from Binary Sorters Using Half Cleaners Reconfigurable Computing and FPGAs (ReConFig)
				[JaSJ17c] T. Jain and K. Schneider and A. Jain Deriving Concentrators from Binary Sorters Using Half Cleaners
				[JaSW17] T. Jain and K. Schneider and F. Walk Out-of-Order Execution of Buffered Function Units in Exposed Data Path Architectures Reconfigurable Architectures Workshop (RAW)
				[LeSc17] A. Legay and K. Schneider Message from the ACSD 2017 Program Chairs Application of Concurrency to System Design (ACSD)
				[ScBr17] K. Schneider and J. Brandt Quartz: A Synchronous Language for Model-based Design of Reactive Embedded Systems
				[TaDS17] J.-P. Talpin and P. Derler and K. Schneider Message from the Chairs Formal Methods and Models for Codesign (MEMOCODE)

2016

				[BhJS16] A. Bhagyanath and T. Jain and K. Schneider Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) Architectures Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[BhSc16] A. Bhagyanath and K. Schneider Optimal Compilation for Exposed Datapath Architectures with Buffered Processing Units by SAT Solvers Formal Methods and Models for Codesign (MEMOCODE)
				[JaSB16] T. Jain and K. Schneider and A. Bhagyanath The Selector-Tree Network: A New Self-Routing and Nonblocking Interconnection Network International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
				[JaSc16] T. Jain and K. Schneider Verifying the Concentration Property of Permutation Networks by BDDs Formal Methods and Models for Codesign (MEMOCODE)
				[LiSc16a] X. Li and K. Schneider Control-flow Guided Clause Generation for Property Directed Reachability High-Level Design Validation and Test Workshop (HLDVT)
				[LiSc16c] X. Li and K. Schneider Control-flow Guided Property Directed Reachability for Synchronous Programs Formal Methods and Models for Codesign (MEMOCODE)
				[RBLS16] T. Ropertz and K. Berns and X. Li and K. Schneider Verification of Behavior-Based Control Systems in their Physical Environment Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[RaSc16] O. Rafique and K. Schneider Introducing MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded Systems International Workshop on Software and Compilers for Embedded Systems (SCOPES)
				[RaSc16a] O. Rafique and K. Schneider Towards the Standardization of Plug-and-Play Devices for Model-Based Designs of Embedded Systems Symposium on Industrial Embedded Systems (SIES)
				[RoSF16] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira Semantics in space systems architectures Innovations in Systems and Software Engineering -- A NASA Journal
				[SeSc16] M. Senftleben and K. Schneider Specifying Weak Memory Consistency with Temporal Logic Verification and Evaluation of Computer and Communication Systems (VECoS)
				[TaLS16] J.P. Talpin and E. Leonard and K. Schneider Welcome Message from the Chairs Formal Methods and Models for Codesign (MEMOCODE)

2015

				[BaSc15] D. Baudisch and K. Schneider Evaluation of Speculation in Out-Of-Order Execution of Synchronous Data-Flow Networks International Journal of Parallel Programming (IJPP)
				[BhJS15] A. Bhagyanath and T. Jain and K. Schneider A Time-Predictable Model of Computation Real-Time Systems Symposium (RTSS)
				[BhSS15] N. Bhardwaj and M. Senftleben and K. Schneider Abacus - A Processor Family for Education Workshop on Embedded and Cyber-Physical Systems Education (WESE)
				[FMSS15] F. Furbach and R. Meyer and K. Schneider and M. Senftleben Memory-Model-aware Testing -- A Unified Complexity Analysis Transactions on Embedded Computing Systems (TECS)
				[LiSc15] X. Li and K. Schneider A Counterexample-Guided Approach to Symbolic Simulation of Hybrid Systems Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[LiSc15a] X. Li and K. Schneider An SMT-based Approach to analyze Non-Linear Relations of Parameters for Hybrid Systems Formal Modeling and Verification of Cyber-Physical Systems
				[LiSc15b] X. Li and K. Schneider Verification Condition Generation for Hybrid Systems Formal Methods and Models for Codesign (MEMOCODE)

2014

				[BSBK14] Y. Bai and K. Schneider and N. Bhardwaj and B. Katti and T. Shazadi From Clock-Driven to Data-Driven Models Formal Methods and Models for Codesign (MEMOCODE)
				[BaBS14] D. Baudisch and Y. Bai and K. Schneider Reducing the Communication of Message-Passing Systems Synthesized from Synchronous Programs Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)
				[BaSc14] Y. Bai and K. Schneider Isochronous Networks by Construction Design, Automation and Test in Europe (DATE)
				[BhSc14] A. Bhagyanath and K. Schneider TTA as Predictable Architecture for Real-Time Applications International Conference on Science, Engineering, Research and Management (ICSEMR)
				[BrSB14] J. Brandt and K. Schneider and Y. Bai Passive Code in Synchronous Programs Transactions on Embedded Computing Systems (TECS)
				[EdGS14] S.A. Edwards and A. Girault and K. Schneider Synchronous Programming (SYNCHRON 2013; Dagstuhl Seminar 13471) Dagstuhl Reports
				[FMSS14] F. Furbach and R. Meyer and K. Schneider and M. Senftleben Memory Model-Aware Testing - A Unified Complexity Analysis Application of Concurrency to System Design (ACSD)
				[GeBS14] M. Gesell and F. Bichued and K. Schneider Using Different Representations of Synchronous Systems in SAL Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[KhBS14] M. Ammar Ben Khadra and Y. Bai and K. Schneider Synthesis of Distributed Synchronous Specifications to SysteMoC Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[KhBS14a] M.A. Ben Khadra and Y. Bai and K. Schneider High Level Modeling of Elastic Circuits in SystemC Symposium on Theory of Modeling and Simulation (TMS/DEVS)
				[LiSc14] X. Li and K. Schneider Interactive Verification of Hybrid Systems Automated Verification of Critical Systems (AVoCS)
				[RoSF14] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira Integrating UML Composite Structures and fUML International Conference on Current Trends in Theory and Practice of Computer Science (SOFSEM)
				[RoSF14a] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira Using the Base Semantics given by fUML for Verification International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
				[ScWi14] K. Schneider and A. Willenbücher A New Algorithm for Carry-Free Addition of Binary Signed-Digit Numbers Field-Programmable Custom Computing Machines (FCCM)
				[TBGS14] J.-P. Talpin and J. Brandt and M. Gemünde and K. Schneider and S. Shukla Constructive Polychronous Systems Science of Computer Programming (SCICO)

2013

				[BGSS13] J. Brandt and M. Gemünde and K. Schneider and S.K. Shukla and J.-P. Talpin Embedding Polychrony into Synchrony IEEE Transactions on Software Engineering (TSE)
				[GeBS13] M. Gemünde and J. Brandt and K. Schneider Clock Refinement in Imperative Synchronous Languages EURASIP Journal on Embedded Systems
				[GeMS13] M. Gesell and A. Morgenstern and K. Schneider Lifting Verification Results for Preemption Statements Software Engineering and Formal Methods (SEFM)
				[GeSc13] M. Gesell and K. Schneider An Interactive Verification Tool for Synchronous/Reactive Systems Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[GeSc13a] M. Gesell and K. Schneider Modular Verification of Synchronous Programs Application of Concurrency to System Design (ACSD)
				[GeSc13c] M. Gesell and K. Schneider Translating synchronous guarded actions to interleaved guarded actions Formal Methods and Models for Codesign (MEMOCODE)
				[LiBS13] X. Li and K. Bauer and K. Schneider Interactive Verification of Cyber-physical Systems: Interfacing Averest and KeYmaera International Workshop on Cyber-Physical Systems (IWCPS)
				[MoGS13] A. Morgenstern and M. Gesell and K. Schneider Solving Games Using Incremental Induction Integrated Formal Methods (IFM)
				[RaGS13] O. Rafique and M. Gesell and K. Schneider Generating hardware specific code at different abstraction levels using Averest International Workshop on Software and Compilers for Embedded Systems (SCOPES)
				[RaGS13a] O. Rafique and M. Gesell and K. Schneider Targeting Different Abstraction Layers by Model-Based Design Methods for Embedded Systems: A Case Study Real-Time Computing Systems and Applications (RTCSA)
				[RaGS13c] O. Rafique and M. Gesell and K. Schneider Learning Various Aspects of a Distributed Real-Time Automotive Embedded System Workshop on Embedded and Cyber-Physical Systems Education (WESE)
				[RoSF13] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira Synchronous Specialization of Alf for Cyber-Physical Systems First Open EIT ICT Labs Workshop on Cyber-Physical Systems Engineering
				[RoSF13a] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira Towards the Applicability of Alf to Model Cyber-Physical Systems International Workshop on Cyber-Physical Systems (IWCPS)
				[TBGS13] J.-P. Talpin and J. Brandt and M. Gemünde and K. Schneider and S. Shukla Constructive Polychronous Systems Logical Foundations of Computer Science (LFCS)
				[WiSc13] A. Willenbücher and K. Schneider Automatic Hard Block Inference on FPGAs Euromicro Conference on Digital System Design

2012

				[BGSS12] J. Brandt and M. Gemünde and K. Schneider and S.K. Shukla and J.-P. Talpin Representation of Synchronous, Asynchronous, and Polychronous Components by Clocked Guarded Actions Design Automation for Embedded Systems (DAEM)
				[BaBS12] D. Baudisch and J. Brandt and K. Schneider Out-Of-Order Execution of Synchronous Data-Flow Networks International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
				[BaBS12a] D. Baudisch and J. Brandt and K. Schneider Efficient Handling of Arrays in Dataflow Process Networks International Conference on Embedded Software and Systems (ICESS)
				[BaBS12b] Y. Bai and J. Brandt and K. Schneider Preservation of LTL Properties in Desynchronized Systems Formal Methods and Models for Codesign (MEMOCODE)
				[BaBS12c] Y. Bai and J. Brandt and K. Schneider Monitoring Distributed Reactive Systems High Level Design Validation and Test Workshop (HLDVT)
				[BaSc12a] K. Bauer and K. Schneider Teaching Cyber-Physical Systems: A Programming Approach Workshop on Embedded and Cyber-Physical Systems Education (WESE)
				[BrSE12] J. Brandt and K. Schneider and S.A. Edwards Translating SHIM to Guarded Actions Technical Report
				[GeSc12] M. Gesell and K. Schneider A Hoare calculus for the verification of synchronous languages Programming Languages meets Program Verification (PLPV)
				[GeSc12a] M. Gesell and K. Schneider Interactive Verification of Synchronous Systems Formal Methods and Models for Codesign (MEMOCODE)
				[MoGS12] A. Morgenstern and M. Gesell and K. Schneider An Asymptotically Correct Finite Path Semantics for LTL Logic for Programming, Artificial Intelligence, and Reasoning (LPAR)

2011

				[BGSS11] J. Brandt and M. Gemünde and K. Schneider and S. Shukla and J.-P. Talpin Integrating System Descriptions by Clocked Guarded Actions Forum on Specification and Design Languages (FDL)
				[BaBS11] Y. Bai and J. Brandt and K. Schneider Data-Flow Analysis of Extended Finite State Machines Application of Concurrency to System Design (ACSD)
				[BaBS11a] Y. Bai and J. Brandt and K. Schneider SMT-Based Optimization for Synchronous Programs Software and Compilers for Embedded Systems (SCOPES)
				[BaBS11b] D. Baudisch and J. Brandt and K. Schneider Translating Synchronous Systems to Data-Flow Process Networks Parallel and Distributed Computing, Applications and Technologies (PDCAT)
				[BaSc11] K. Bauer and K. Schneider Transferring Causality Analysis from Synchronous Programs to Hybrid Programs International Modelica Conference
				[BrSc11] J. Brandt and K. Schneider Round Trip to Asynchrony and Synchrony Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[BrSc11a] J. Brandt and K. Schneider Separate Translation of Synchronous Programs to Guarded Actions Technical Report
				[GeBS11] M. Gemünde and J. Brandt and K. Schneider Schizophrenia and Causality in the Context of Refined Clocks Forum on Specification and Design Languages (FDL)
				[GeBS11a] M. Gemünde and J. Brandt and K. Schneider Causality Analysis of Synchronous Programs with Refined Clocks High Level Design Validation and Test Workshop (HLDVT)
				[HGPB11] K. Heckemann and M. Gesell and T. Pfister and K. Berns and K. Schneider and M. Trapp Safe Automotive Software Knowledge-Based and Intelligent Information and Engineering Systems (KES)
				[MoSc11] A. Morgenstern and K. Schneider Synthesis of Parallel Sorting Networks using SAT Solvers Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[MoSc11a] A. Morgenstern and K. Schneider A LTL Fragment for $ GR (1)$-Synthesis International Workshop on Interactions, Games and Protocols (IWIGP)
				[MoSc11b] A. Morgenstern and K. Schneider Program Sketching via CTL* Model Checking Model Checking Software (SPIN)

2010

				[BSAS10] J. Brandt and K. Schneider and S. Ahuja and S.K. Shukla The Model Checking View to Clock Gating and Operand Isolation Application of Concurrency to System Design (ACSD)
				[BaBS10] D. Baudisch and J. Brandt and K. Schneider Multithreaded Code from Synchronous Programs: Extracting Independent Threads for OpenMP Design, Automation and Test in Europe (DATE)
				[BaBS10a] D. Baudisch and J. Brandt and K. Schneider Multithreaded Code from Synchronous Programs: Generating Software Pipelines for OpenMP Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[BaBS10b] D. Baudisch and J. Brandt and K. Schneider Dependency-Driven Distribution of Synchronous Programs Distributed and Parallel Embedded Systems (DIPES)
				[BaGS10] K. Bauer and R. Gentilini and K. Schneider A Uniform Approach to Three-Valued Semantics for mu-Calculus on Abstractions of Hybrid Automata Software Tools for Technology Transfer (STTT)
				[BaSc10] K. Bauer and K. Schneider From synchronous programs to symbolic representations of hybrid systems Hybrid Systems: Computation and Control (HSCC)
				[BaSc10a] K. Bauer and K. Schneider Predicting Events for the Simulation of Hybrid Systems International Conference on Computer and Information Technology (CIT)
				[BrGS10] J. Brandt and M. Gemünde and K. Schneider From Synchronous Guarded Actions to SystemC Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[BrSS10] J. Brandt and K. Schneider and S.K. Shukla Translating concurrent action oriented specifications to synchronous guarded actions Languages, Compilers, and Tools for Embedded Systems (LCTES)
				[GeBS10] M. Gemünde and J. Brandt and K. Schneider Clock Refinement in Imperative Synchronous Languages SYNCHRON'09: Abstracts Collection of Dagstuhl Seminar 09481
				[GeBS10a] M. Gemünde and J. Brandt and K. Schneider A Formal Semantics of Clock Refinement in Imperative Synchronous Languages Application of Concurrency to System Design (ACSD)
				[GeBS10b] M. Gemünde and J. Brandt and K. Schneider Compilation of Imperative Synchronous Programs with Refined Clocks Formal Methods and Models for Codesign (MEMOCODE)
				[MoSc10] A. Morgenstern and K. Schneider Exploiting the Temporal Logic Hierarchy and the Non-Confluence Property for Efficient LTL Synthesis Games, Automata, Logics, and Formal Verification (GandALF)

2009

				[BaGS09] D. Baudisch and M. Gesell and K. Schneider Online Exercise System -- A Web-Based Tool for Administration and Automatic Correction of Exercises Computer Supported Education (CSEDU)
				[BaGS09a] K. Bauer and R. Gentilini and K. Schneider Property Driven Three-Valued Model Checking on Hybrid Automata Workshop on Logic, Language, Information and Computation (WoLLIC)
				[BaGS09b] K. Bauer and R. Gentilini and K. Schneider A Uniform Approach to Three-Valued Semantics for mu-Calculus on Abstractions of Hybrid Automata Haifa Verification Conference (HVC)
				[BrGS09] J. Brandt and M. Gemünde and K. Schneider Desynchronizing Synchronous Programs by Modes Application of Concurrency to System Design (ACSD)
				[BrSW09] J. Brandt and K. Schneider and A. Willenbücher Using IP Cores in Synchronous Languages Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[BrSc09] J. Brandt and K. Schneider Separate Compilation for Synchronous Programs Software and Compilers for Embedded Systems (SCOPES)
				[BrSc09a] J. Brandt and K. Schneider Static Data-Flow Analysis of Synchronous Programs Formal Methods and Models for Codesign (MEMOCODE)
				[Schn09] K. Schneider The Synchronous Programming Language Quartz Technical Report
				[VeTS09] E. Vecchié and J.-P. Talpin and K. Schneider Separate Compilation and Execution of Imperative Synchronous Modules Design, Automation and Test in Europe (DATE)

2008

				[BaGS08] K. Bauer and R. Gentilini and K. Schneider Approximated Reachability on Hybrid Automata: Falsification meets Certification Electronic Notes in Theoretical Computer Science (ENTCS)
				[BrSW08] J. Brandt and K. Schneider and A. Willenbücher Hardware Acceleration for Model Checking Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[BrSc08] J. Brandt and K. Schneider Embedded Systems: Status and Perspective
				[BrSc08a] J. Brandt and K. Schneider Formal Reasoning About Causality Analysis Theorem Proving in Higher Order Logics (TPHOL)
				[MoSL08] A. Morgenstern and K. Schneider and S. Lamberti Generating Deterministic $\omega$-Automata for most LTL Formulas by the Breakpoint Construction Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[MoSc08] A. Morgenstern and K. Schneider From LTL to Symbolically Represented Deterministic Automata Verification, Model Checking, and Abstract Interpretation (VMCAI)
				[PoSc08] A. Poetzsch-Heffter and K. Schneider Workshop on Verification of Adaptive Systems (VerAS) Electronic Notes in Theoretical Computer Science (ENTCS)
				[ScBr08] K. Schneider and J. Brandt Performing Causality Analysis by Bounded Model Checking Application of Concurrency to System Design (ACSD)

2007

				[BrSc07] J. Brandt and K. Schneider Different Kinds of System Descriptions as Synchronous Programs
				[BrSc07b] J. Brandt and K. Schneider How Different are Esterel and SystemC? Forum on Specification and Design Languages (FDL)
				[GeSD07a] R. Gentilini and K. Schneider and A. Dreyer Combining Interval Arithmetic and Three-Valued Temporal Logics for the Verification of Analog Systems Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[GeSD07b] R. Gentilini and K. Schneider and A. Dreyer Three-Valued Automated Reasoning on Analog Properties Great Lakes Symposium on VLSI (GLSVLSI)
				[GeSM07] R. Gentilini and K. Schneider and B. Mishra Successive Abstractions of Hybrid Automata for Monotonic CTL Model Checking Logical Foundations of Computer Science (LFCS)
				[MoSc07] A. Morgenstern and K. Schneider Synthesizing Deterministic Controllers in Supervisory Control Informatics in Control, Automation and Robotics (ICINCO)
				[PBSS07] M. Proetzsch and K. Berns and T. Schüle and K. Schneider Formal Verification of Safety Behaviours of the Outdoor Robot RAVON Informatics in Control, Automation and Robotics (ICINCO)
				[PoSc07] A. Poetzsch-Heffter and K. Schneider First DASMOD Workshop on Verification of Adaptive Systems (VerAS) Technical Report
				[ScBr07a] K. Schneider and J. Brandt Theorem Proving in Higher Order Logics and Applications -- Emerging Trends Technical Report
				[ScSc07] T. Schüle and K. Schneider Verification of Data Paths Using Unbounded Integers: Automata Strike Back Haifa Verification Conference (HVC)
				[ScSc07a] T. Schüle and K. Schneider Bounded Model Checking of Infinite State Systems Formal Methods in System Design (FMSD)
				[TuSG07] T. Türk and K. Schneider and M. Gordon Model Checking PSL Using HOL and SMV Haifa Verification Conference (HVC)

2006

				[BrSc06a] J. Brandt and K. Schneider System Description Aspects as Syntactic Sugar Forum on Specification and Design Languages (FDL)
				[BrSc06b] J. Brandt and K. Schneider Efficient Map Overlay for Safety-Critical Embedded Systems Industrial Embedded Systems (IES)
				[ScBS06] K. Schneider and J. Brandt and T. Schüle A Verified Compiler for Synchronous Programs with Local Declarations Electronic Notes in Theoretical Computer Science (ENTCS)
				[ScBV06a] K. Schneider and J. Brandt and E. Vecchié Modular Compilation of Synchronous Programs Distributed and Parallel Embedded Systems (DIPES)
				[ScBV06b] K. Schneider and J. Brandt and E. Vecchié Efficient Code Generation from Synchronous Programs Formal Methods and Models for Codesign (MEMOCODE)
				[ScST06] K. Schneider and T. Schüle and M. Trapp Verifying the Adaptation Behavior of Embedded Systems Software Engineering for Adaptive and Self-Managing Systems (SEAMS)
				[ScSc06a] K. Schneider and T. Schüle A Framework for Verifying and Implementing Embedded Systems Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[Schn06a] K. Schneider Book Review: `A Practical Theory of Reactive Systems' The Computer Journal

2005

				[BrSc05] J. Brandt and K. Schneider Using Three-Valued Logic to Specify and Verify Algorithms of Computational Geometry International Conference on Formal Engineering Methods (ICFEM)
				[BrSc05a] J. Brandt and K. Schneider Dependable Polygon-Processing Algorithms for Safety-Critical Embedded Systems Embedded and Ubiquitous Computing (EUC)
				[MoSc05] A. Morgenstern and K. Schneider A Unified Model Checking Framework for the Supervisor Synthesis Problem Games for Logic and Programming Languages
				[MoSc05a] A. Morgenstern and K. Schneider Synthesizing Deterministic Controllers in Supervisory Control Informatics in Control, Automation and Robotics (ICINCO)
				[MoSc05b] A. Morgenstern and K. Schneider Using Model Checking to Solve Supervisor Synthesis Problems Conference on Decision and Control and European Control Conference (CDC/ECC)
				[SBST05a] K. Schneider and J. Brandt and T. Schüle and T. Türk Improving Constructiveness in Code Generators Synchronous Languages, Applications, and Programming (SLAP)
				[SBST05b] K. Schneider and J. Brandt and T. Schüle and T. Türk Maximal Causality Analysis Application of Concurrency to System Design (ACSD)
				[ScSc05] T. Schüle and K. Schneider Three-Valued Logic in Bounded Model Checking Formal Methods and Models for Codesign (MEMOCODE)
				[ScSc05a] K. Schneider and T. Schüle Averest: Specification, Verification, and Implementation of Reactive Systems Application of Concurrency to System Design (ACSD)
				[TuSc05] T. Türk and K. Schneider From PSL to LTL: A Formal Validation in HOL Theorem Proving in Higher Order Logics (TPHOL)
				[TuSc05a] T. Türk and K. Schneider Relationship between Alternating omega-Automata and Symbolically Represented Nondeterministic omega-Automata Technical Report
				[ZiSc05] R. Ziller and K. Schneider Combining Supervisor Synthesis and Model Checking ACM Transactions on Embedded Computing Systems (TECS)

2004

				[BuKS04] W. Büttner and W. Kunz and K. Schneider Verifikation reaktiver Systeme
				[ScBS04a] K. Schneider and J. Brandt and T. Schüle A Verified Compiler for Synchronous Programs with Local Declarations (proceedings version) Synchronous Languages, Applications, and Programming (SLAP)
				[ScBS04b] K. Schneider and J. Brandt and T. Schüle Causality Analysis of Synchronous Programs with Delayed Actions Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
				[ScSc04] T. Schüle and K. Schneider Global vs. Local Model Checking of Infinite State Systems Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[ScSc04a] T. Schüle and K. Schneider Abstraction of Assembler Programs for Symbolic Worst Case Execution Time Analysis Design Automation Conference (DAC)
				[ScSc04b] T. Schüle and K. Schneider Bounded Model Checking of Infinite State Systems: Exploiting the Automata Hierarchy Formal Methods and Models for Codesign (MEMOCODE)
				[ScSc04c] T. Schüle and K. Schneider Global vs. Local Model Checking: A Comparison of Verification Techniques for Infinite State Systems Software Engineering and Formal Methods (SEFM)

2003

				[LoSM03a] G. Logothetis and K. Schneider and C. Metzler Exact Low-Level Runtime Analysis of Synchronous Programs for Formal Verification of Real-Time Systems Forum on Specification and Design Languages (FDL)
				[LoSM03b] G. Logothetis and K. Schneider and C. Metzler Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification Symposium on Integrated Circuits and System Design (SBCCI)
				[LoSM03c] G. Logothetis and K. Schneider and C. Metzler Generating Formal Models for Real-Time Verification by Exact Low-Level Runtime Analysis of Synchronous Programs Real-Time Systems Symposium (RTSS)
				[LoSc03] G. Logothetis and K. Schneider Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration Design, Automation and Test in Europe (DATE)
				[ScSc03] T. Schüle and K. Schneider Exact Runtime Analysis Using Automata-Based Symbolic Simulation Formal Methods and Models for Codesign (MEMOCODE)
				[Schn03] K. Schneider Verification of Reactive Systems -- Formal Methods and Algorithms Springer
				[ZiSc03a] R.M. Ziller and K. Schneider A $\mu$-Calculus Approach to Supervisor Synthesis Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[ZiSc03b] R. Ziller and K. Schneider A Generalized Approach to Supervisor Synthesis Formal Methods and Models for Codesign (MEMOCODE)
				[ZiSc03c] R. Ziller and K. Schneider Reducing Complexity of Supervisor Synthesis Control Systems Design (CSD)

2002

				[BaSc02] M. Baldamus and K. Schneider The BDD Space Complexity of Different Forms of Concurrency Fundamenta Informaticae
				[LoSc02] G. Logothetis and K. Schneider Extending Synchronous Languages for Generating Abstract Real-Time Models Design, Automation and Test in Europe (DATE)
				[ScSc02] T. Schüle and K. Schneider Symbolic Model Checking by Automata Based Set Representation Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[Schn02] K. Schneider Proving the Equivalence of Microstep and Macrostep Semantics Theorem Proving in Higher Order Logics (TPHOL)

2001

				[BSWZ01] M. Baldamus and K. Schneider and M. Wenz and R. Ziller Can American Checkers be Solved by Means of Symbolic Model Checking? Electronic Notes in Theoretical Computer Science (ENTCS)
				[BaSc01] M. Baldamus and K. Schneider The BDD Space Complexity of Different Forms of Concurrency Application of Concurrency to System Design (ACSD)
				[HHKK01] D.W. Hoffmann and L. Holt and E. Klein and T. Kropf and K. Schneider Special Issue on the PROSPER project
				[LoSc01] G. Logothetis and K. Schneider A New Approach to the Specification and Verification of Real-Time Systems Euromicro Conference on Real-Time Systems (ECRTS)
				[LoSc01a] G. Logothetis and K. Schneider Symbolic model checking of real-time systems Temporal Representation and Reasoning (TIME)
				[ScWe01] K. Schneider and M. Wenz A new method for compiling schizophrenic synchronous programs Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
				[Schn01] K. Schneider Exploiting Hierarchies in Temporal Logics, Finite Automata, Arithmetics, and $\mu$-Calculus for Efficiently Verifying Reactive Systems Habilitation Thesis
				[Schn01a] K. Schneider Embedding Imperative Synchronous Languages in Interactive Theorem Provers Application of Concurrency to System Design (ACSD)
				[Schn01b] K. Schneider Improving Automata Generation for Linear Temporal Logic by Considering the Automata Hierarchy Logic for Programming, Artificial Intelligence, and Reasoning (LPAR)

2000

				[BSWZ00] M. Baldamus and K. Schneider and M. Wenz and R. Ziller Can American Checkers be Solved by Means of Symbolic Model Checking? Formal Methods Elsewhere
				[LoSc00] G. Logothetis and K. Schneider Abstraction from Counters: An Application on Real-Time Systems Design, Automation and Test in Europe (DATE)
				[Schn00] K. Schneider A Verified Hardware Synthesis for Esterel Distributed and Parallel Embedded Systems (DIPES)

1999

				[BaSc99] M. Baldamus and K. Schneider Extending Esterel by Asynchronous Concurrency Fachtagung zum Entwurf Integrierter Schaltungen
				[HSKL99] M. Huhn and K. Schneider and T. Kropf and G. Logothetis Verifying Imprecisely Working Arithmetic Circuits Design, Automation and Test in Europe (DATE)
				[SSHL99] D. Schmid and K. Schneider and M. Huhn and G. Logothetis and V. Sabelfeld Formale Verifikation eingebetteter Systeme Informationstechnik und Technische Informatik (it+ti)
				[ScHL99] K. Schneider and M. Huhn and G. Logothetis Validation of Object Oriented Concurrent Designs by Model Checking Correct Hardware Design and Verification Methods (CHARME)
				[ScHL99a] K. Schneider and M. Huhn and G. Logothetis Validation of Object Oriented Concurrent Designs by Model Checking
				[ScHo99] K. Schneider and D.W. Hoffmann A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata Theorem Proving in Higher Order Logics (TPHOL)
				[ScHu99] K. Schneider and M. Huhn Comparing Model-Checking and Term-Rewriting in the Verification of an Embedded System Distributed and Parallel Embedded Systems (DIPES)
				[ScLo99] K. Schneider and G. Logothetis Abstraction of Systems with Counters for Symbolic Model Checking Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[ScSa99] K. Schneider and V. Sabelfeld Introducing Mutual Exclusion in Esterel Andrei Ershov Third International Conference Perspectives of Systems Informatics
				[Schn99] K. Schneider Yet Another Look at LTL Model Checking Correct Hardware Design and Verification Methods (CHARME)
				[StSH99] T. Stauner and K. Schneider and M. Huhn Translating a Visual Description Technique to a Synchronous Language: From DiCharts to PURR Formale Beschreibungstechniken für verteilte Systeme

1998

				[GrSc98] W. Grünewald and K. Schneider Modeling and Verifying Abstract Multithreaded Systems Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[KRSW98] T. Kropf and J. Ruf and K. Schneider and M. Wild A Synchronous Language for Modeling and Verifying Real Time and Embedded Systems Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[KRSW98a] T. Kropf and J. Ruf and K. Schneider and M. Wild The Synchronous System Description Language PURR System Design Automation
				[ReSK98] R. Reetz and K. Schneider and T. Kropf Formal Specification in VHDL for Formal Hardware Verification Design, Automation and Test in Europe (DATE)
				[SSFS98] I. Schreiber and J. Schönherr and E. Fordran and K. Schneider and B. Straube Kontrollfluss-Verifikation von Algorithmen mittels Modellprüfung Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
				[Schn98] K. Schneider Model Checking on Product Structures Formal Methods in Computer-Aided Design (FMCAD)

1997

				[ReSK97a] R. Reetz and K. Schneider and T. Kropf Formale Spezifikation und Verifikation mit VHDL Hardwarebeschreibungssprachen und Modellierungsparadigmen
				[ReSK97b] R. Reetz and K. Schneider and T. Kropf Ein neues Konzept zur formalen Spezifikation in VHDL mit einer Fallstudie zum Single Pulser Methoden des Entwurfs und der Verifikation digitaler Systeme
				[ScKr97a] K. Schneider and T. Kropf The C@S System: Combining Proof Strategies for System Verification
				[ScWe97] K. Schneider and H. Weindel An Efficient Decision Procedure for S1S Methoden des Entwurfs und der Verifikation digitaler Systemen (GI/ITG/GMM Workshop)
				[Schn97b] K. Schneider Translating LTL to Deterministic Omega-Automata Methoden des Entwurfs und der Verifikation digitaler Systemen (GI/ITG/GMM Workshop)

1996

				[FrKS96] J. Frößl and T. Kropf and K. Schneider Bewertung temporaler Logiken für die Hardware-Verifikation Methoden des Entwurfs und der Verifikation digitaler Systeme (GI/ITG/GME Workshop)
				[ScKr96b] K. Schneider and T. Kropf A Unified Approach for Combining Different Formalisms for Hardware Verification Methoden des Entwurfs und der Verifikation digitaler Systeme (GI/ITG/GME Workshop)
				[ScKr96c] K. Schneider and T. Kropf A Unified Approach for Combining Different Formalisms for Hardware Verification Formal Methods in Computer-Aided Design (FMCAD)
				[Schn96a] K. Schneider Ein einheitlicher Ansatz zur Unterstützung von Abstraktionsmechanismen der Hardwareverifikation Infix

1995

				[KrSK95] T. Kropf and K. Schneider and R. Kumar A Formal Framework for High Level Synthesis Theorem Provers in Circuit Design (TPCD)
				[ScKT95b] K. Schneider and T. Kropf and T. Thiessenhusen Spezifikation und Verifikation systolischer Felder mit Logik höherer Ordnung Anwendung formaler Methoden beim Entwurf von Hardwaresystemen
				[Schn95c] K. Schneider Ein automatentheoretischer Ansatz zur Strukturabstraktion für die hierarchische Verifikation Anwendung formaler Methoden beim Entwurf von Hardwaresystemen

1994

				[EiSK94] D. Eisenbiegler and K. Schneider and R. Kumar A Functional Approach for Formalizing Regular Hardware Structures Theorem Proving in Higher Order Logics (TPHOL)
				[PoSc94] J. Posegga and K. Schneider A First-Order Calculus Based on Propositional BDDs Anwendung formaler Methoden im Systementwurf
				[SSSK94] A. Schneider and B. Straube and K. Schneider and T. Kropf Verifikation eines digitalen Netzwerkes mit Hilfe des Beweissystems HOL Technical Report
				[ScKK94] K. Schneider and R. Kumar and T. Kropf Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification Theorem Proving in Higher Order Logics (TPHOL)
				[ScKK94a] K. Schneider and T. Kropf and R. Kumar Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path European Design Automation Conference (EDAC)
				[ScKK94b] K. Schneider and T. Kropf and R. Kumar Accelerating Tableaux Proofs using Compact Representations Formal Methods in System Design (FMSD)
				[ScKK94c] K. Schneider and T. Kropf and R. Kumar Why Hardware Verification Needs more than Model Checking Theorem Proving in Higher Order Logics (TPHOL)
				[ScKK94d] K. Schneider and R. Kumar and T. Kropf Automating Verification by Functional Abstraction at the System Level Theorem Proving in Higher Order Logics (TPHOL)
				[ScKK94e] K. Schneider and R. Kumar and T. Kropf Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic Theorem Proving in Higher Order Logics (TPHOL)
				[ScKK94h] K. Schneider and T. Kropf and R. Kumar Hardware-Verifikation braucht mehr als Model-Checking Anwendung formaler Methoden im Systementwurf

1993

				[KrKS93a] T. Kropf and R. Kumar and K. Schneider Embedding Hardware Verification within a Commercial Design Framework Correct Hardware Design and Verification Methods (CHARME)
				[KuSK93a] R. Kumar and K. Schneider and T. Kropf Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment Formal Methods in System Design (FMSD)
				[PoSc93] J. Posegga and K. Schneider Deduction with First-Order BDDs Theorem Proving with Analytic Tableaux and Related Methods (TABLEAUX)
				[ScKK93a] K. Schneider and R. Kumar and T. Kropf Hardware-Verification using First Order BDDs Computer Hardware Description Languages and Their Applications (CHDL)
				[ScKK93e] K. Schneider and T. Kropf and R. Kumar Kontrollpfad-orientierte Verifikation generischer Datenpfade Entwurf integrierter Schaltungen (EIS)
				[ScRS93] D. Schmid and R. Reetz and K. Schneider Ein Praktikum zur Hardware-Verifikation Entwurf integrierter Schaltungen (EIS)

1992

				[ScKK92] K. Schneider and R. Kumar and T. Kropf Automating most Parts of Hardware Proofs in HOL Computer Aided Verification (CAV)
				[ScKK92a] K. Schneider and R. Kumar and T. Kropf The FAUST Prover Conference on Automated Deduction (CADE)
				[ScKK92b] K. Schneider and R. Kumar and T. Kropf Efficient Representation and Computation of Tableau Proofs Theorem Proving in Higher Order Logics (TPHOL)
				[ScKK92c] K. Schneider and R. Kumar and T. Kropf Modelling generic Hardware Structures by Abstract Datatypes Theorem Proving in Higher Order Logics (TPHOL)

1991

				[KuKS91a] R. Kumar and T. Kropf and K. Schneider Integrating a First-Order Automatic Prover in the HOL Environment Theorem Proving in Higher Order Logics (TPHOL)
				[KuKS91b] R. Kumar and T. Kropf and K. Schneider First Steps Towards Automating Hardware Proofs in HOL Theorem Proving in Higher Order Logics (TPHOL)
				[ScKK91a] K. Schneider and R. Kumar and T. Kropf Structuring Hardware Proofs: First steps towards Automation in a Higher-Order Environment Very Large Scale Integration (VLSI)
				[Schn91] K. Schneider Ein Sequenzenkalkül für HOL Master Thesis