|
|
|
 
|
[Bitt24]
C. Bittes
An Evaluation of Cold Boot Attacks
|
|
|
|
 
|
[Bitt24a]
C. Bittes
An Evaluation of Cold Boot Attacks
|
|
|
|
 
|
[Chee24]
A.U. Cheema
Fault Attacks
|
|
|
|
 
|
[Chee24a]
A.U. Cheema
Fault Attacks
|
|
|
|
 
|
[Chri24]
K. Christmann
Power Side-Channel Attacks
|
|
|
|
 
|
[Chri24a]
K. Christmann
Power Side-Channel Attacks
|
|
|
|
 
|
[Fass24]
A. Faßbender
Empirische Evaluierung der Effekte von Hardwarebeschleunigung auf quantenresistente Kryptographie im TLS 1.3 Protokoll
Bachelor Thesis
|
|
|
|
 
|
[Geup24]
H. Geupel
Mitigating Branch Prediction Attacks - A Comparison
|
|
|
|
 
|
[Geup24a]
H. Geupel
Mitigating Branch Prediction Attacks - A Comparison
|
|
|
|
 
|
[Hemm24]
L. Hemmerling
Hardware-based Control-Flow Integrity: An Overview
|
|
|
|
 
|
[Hemm24a]
L. Hemmerling
Hardware-based Control-Flow Integrity: An Overview
|
|
|
|
 
|
[Jose24]
A.P. Jose
A Microkernel based solution for SAFE Deadline Monitoring
Master Thesis
|
|
|
|
 
|
[Kapl24]
T. Kaplan
Firmware Vulnerabilities
|
|
|
|
 
|
[Kapl24a]
T. Kaplan
Firmware Vulnerabilities
|
|
|
|
 
|
[KrSc24]
F. Krebs and K. Schneider
Memory Footprint Reduction for Dataflow Process Networks using Virtual Channels
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[Luet24]
A. Lütke-Bordewick
Physical Unclonable Functions: Use Cases, Implementations and Exploits
|
|
|
|
 
|
[Luet24a]
A. Lütke-Bordewick
Physical Unclonable Functions: Use Cases, Implementations and Exploits
|
|
|
|
 
|
[Ried24]
S. Riedel
A Survey about Acoustic and Electromagnetic Attacks and other Physical Side Channels
|
|
|
|
 
|
[Ried24a]
S. Riedel
A Survey about Acoustic and Electromagnetic Attacks and other Physical Side Channels
|
|
|
|
 
|
[Saji24]
K.B. Sajikumar
Modeling Hazardous Events in Automated Driving for Probabilistic Approach of Test Instrumentation
Master Thesis
|
|
|
|
 
|
[Stra24a]
T.-F. Straub
Hardware trojans
|
|
|
|
 
|
[Stra24b]
T.-F. Straub
Hardware trojans
|
|
|
|
 
|
[Tego24]
F. Tego
Efficient Translation of Linear Temporal Logic to Deterministic Automata
Master Thesis
|
|
|
|
 
|
[WeSc24a]
M.C. Werner and K. Schneider
From Imperative Sequential Structured Text Models to Synchronous Quartz and Sequentially Constructive Models
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[WeSc24b]
M.C. Werner and K. Schneider
PLCreX -- Open-Source Project for Simplification, Transformation, Analysis, and Validation of Programmable Logic Controllers
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[WeSc24c]
M.C. Werner and K. Schneider
From Imperative Sequential Structured Text Models to Synchronous Quartz and Sequentially Constructive Models
Presentation
|
|
|
|
 
|
[WeSc24d]
M.C. Werner and K. Schneider
PLCreX -- Open-Source Project for Simplification, Transformation, Analysis, and Validation of Programmable Logic Controllers
Presentation
|
|
|
|
 
|
[BKMJ23]
E. Borth and S. Klaaßen and F. Mbikhoum and A.P. Jose
Report on OpenMP Project
|
|
|
|
 
|
[BhKS23]
A. Bhagyanath and N. Kercher and K. Schneider
Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann Architectures
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[BhSc23]
A. Bhagyanath and K. Schneider
Program Balancing in Compilation for Buffered Hybrid Dataflow Processors
Computer Architectures and Platforms at Computer Software and Applications Conference (CAP@COMPSAC)
|
|
|
|
 
|
[Bort23]
E. Borth
Generating parallel OpenCL and OpenMP Programs from Dataflow Graphs
Bachelor Thesis
|
|
|
|
 
|
[Bort23a]
E. Borth
Generating parallel OpenCL and OpenMP Programs from Dataflow Graphs
Presentation
|
|
|
|
 
|
[Diet23]
F. Dietrich
Is the future all optical?
|
|
|
|
 
|
[Diet23a]
F. Dietrich
Tail Duplication for Compilation for Buffered Exposed Datapath Architectures
Bachelor Thesis
|
|
|
|
 
|
[Ejla23]
N. Ejlali
Representing threat models by the Open Security Controls Assessment Language (OSCAL)
Master Thesis
|
|
|
|
 
|
[Frei23]
J. Freiermuth
Echtzeit-Schaltassistent fü̈r Elektrofahrzeuge mit Schaltgetriebe
Master Thesis
|
|
|
|
 
|
[Frie23]
E. Friedek
A Study of Coarse-Grained Reconfigurable Architectures
|
|
|
|
 
|
[Gupt23]
A. Gupta
A Model Driven Migration of Complex Legacy Solutions to a new ABAP software stack
Master Thesis
|
|
|
|
 
|
[Haeu23]
M. Häuser
Designing a Secure and Space-Efficient Executable File Format for the Unified Extensible Firmware Interface
Master Thesis
|
|
|
|
 
|
[Kerc23]
N. Kercher
Code Generation for Buffered Exposed Datapath Architectures
Master Thesis
|
|
|
|
 
|
[Kozi23]
S. Koziakov
Towards a safe user-level virtual machine monitor for L4Re
Master Thesis
|
|
|
|
 
|
[Kuag23]
M. Kuaguim
Synchronous Language Approaches: An Overview
|
|
|
|
 
|
[Misr23]
S. Misra
Power-Efficient Computing Strategies: Exploring DVFS, DPM, and Aggressive Scheduling for Enhanced Performance and Energy Savings
|
|
|
|
 
|
[Neuh23]
Y. Neuhard
Developing an Augmented Reality Solution with GPU/CUDA Support to Evaluate and Visualize V2X Scenarios in a Driving Vehicle
Master Thesis
|
|
|
|
 
|
[Pola23]
P.J. Polavarapu
A Survey of Tiny Processors
|
|
|
|
 
|
[RoBS23]
J. Roob and A. Bhagyanath and K. Schneider
Towards Buffers as a Scalable Alternative to Registers for Processor-Local Memory
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[ScBh23]
K. Schneider and A. Bhagyanath
Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann Architectures
Transactions on Embedded Computing Systems (TECS)
|
|
|
|
 
|
[Schr23]
E. Schreiner
Using Dataflow Models for Real-Time Systems
|
|
|
|
 
|
[Sonn23]
L. Sonnenfeld
FPGA Graphics: A Proposition for a Graphics Pipeline Architecture for FPGAs
|
|
|
|
 
|
[ThSc23]
D. Theis and K. Schneider
Towards a Basis for Endochronous Functions in Dataflow Process Networks
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[WeRS23]
L. Werner and J. Roob and K. Schneider
Network-On-Chip Performance Evaluation by Synchronous Circuit Simulation
Network on Chip Architectures (NoCArc)
|
|
|
|
 
|
[WeSc23]
M.C. Werner and K. Schneider
Formal Methods-based Optimization of Dataflow Models with Translation to Synchronous Models
Forum on Specification and Design Languages (FDL)
|
|
|
|
 
|
[Wern23]
L. Werner
Performance Evaluation of Interconnection Networks on Processors
Bachelor Thesis
|
|
|
|
 
|
[Zeun23]
J. Zeunert
Assessing the Security of Integrating SystemVerilog Synthesis and Simulation in Untrusted Environments
Master Thesis
|
|
|
|
 
|
[Balk22]
D. Balke
Consistency and Robustness in an Event-sourced System
Bachelor Thesis
|
|
|
|
 
|
[BhSc22]
A. Bhagyanath and K. Schneider
Buffer Allocation for Exposed Datapath Architectures
International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
|
|
|
|
 
|
[BhSc22a]
A. Bhagyanath and K. Schneider
Buffer Allocation for Exposed Datapath Architectures
Presentation
|
|
|
|
 
|
[Burg22]
T. Burgers
A Study on the Model-based Development of Automotive Software
|
|
|
|
 
|
[Chri22]
F. Christoph
Lambda Calculus and How It Shapes Programming Languages Today
|
|
|
|
 
|
[Goeb22]
P. Göbel
Methoden zur Prozessorverifikation und zum Testen
|
|
|
|
 
|
[Haeu22]
M. Häuser
Use of Symbolic Execution for Verification
|
|
|
|
 
|
[Luet22]
A.D. Lütke-Bordewick
Instruction Scheduling for Exposed Datapath Architectures
Bachelor Thesis
|
|
|
|
 
|
[Mahm22]
H.M.A. Mahmoud
Mapping Dataflow Process Networks on Real-time Operating Systems
Bachelor Thesis
|
|
|
|
 
|
[Nand22]
M. Nandanwar
Formal Verification with Petri Nets
|
|
|
|
 
|
[Nara22]
S.S. Naragund
Sequencing Constraints in Contract-based verification
Master Thesis
|
|
|
|
 
|
[Nara22a]
A. Narasimhan
Evaluation of Binary Moment Diagrams
Master Thesis
|
|
|
|
 
|
[Neuh22]
Y. Neuhard
A Comparison of Real-time Operating Systems for Embedded Computing
|
|
|
|
 
|
[RaSc22]
O. Rafique and K. Schneider
Data-aware Global Scheduling of Dataflow Process Networks
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[RaSc22a]
O. Rafique and K. Schneider
Data-aware Global Scheduling of Dataflow Process Networks
Presentation
|
|
|
|
 
|
[RaSc22b]
O. Rafique and K. Schneider
Synthesis of Parallel Software from Heterogeneous Dataflow Models
Springer Nature Computer Science (SNCS)
|
|
|
|
 
|
[Rame22]
R. Ramesh
Decompilation of Move Programs to Dataflow Process Networks
Master Thesis
|
|
|
|
 
|
[ScBR22]
K. Schneider and A. Bhagyanath and J. Roob
Virtual Buffers for Exposed Datapath Architectures
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[ScBR22a]
K. Schneider and A. Bhagyanath and J. Roob
Virtual Buffers for Exposed Datapath Architectures
Presentation
|
|
|
|
 
|
[ScBR22b]
K. Schneider and A. Bhagyanath and J. Roob
Code Generation Criteria for Buffered Exposed Datapath Architectures from Dataflow Graphs
Languages, Compilers, and Tools for Embedded Systems (LCTES)
|
|
|
|
 
|
[ScBR22c]
K. Schneider and A. Bhagyanath and J. Roob
Code Generation Criteria for Buffered Exposed Datapath Architectures from Dataflow Graphs
Presentation
|
|
|
|
 
|
[Scha22]
O. Schauer
SATA and Beyond: Overview of Storage Hardware Interfaces
|
|
|
|
 
|
[Schi22]
E. Schiebelbein
The Multi-Paradigm Synchronous Programming Language LEA
|
|
|
|
 
|
[Thei22]
D. Theis
Symbolic Execution of Synchronous Quartz Programs
Master Thesis
|
|
|
|
 
|
[Upad22]
S. Upadhye
Data-Driven System Design Based on the Development Data
Master Thesis
|
|
|
|
 
|
[WeSc22]
M.C. Werner and K. Schneider
From IEC 61131-3 Function Block Diagrams to Sequentially Constructive Statecharts
Forum on Specification and Design Languages (FDL)
|
|
|
|
 
|
[WeSc22a]
M.C. Werner and K. Schneider
From IEC 61131-3 Function Block Diagrams to Sequentially Constructive Statecharts
Presentation
|
|
|
|
 
|
[Wern22]
L. Werner
s
|
|
|
|
 
|
[BaRS21]
Y. Bai and O. Rafique and K. Schneider
A Model-based Design Flow for Asynchronous Implementations from Synchronous Specifications
Design, Automation and Test in Europe (DATE)
|
|
|
|
 
|
[Dahl21]
M. Dahlem
Using Enhanced Logic Programming Semantics for Extending and Optimizing Synchronous System Design
PhD Thesis
|
|
|
|
 
|
[Feth21]
M.T. Feth
A Resource-Constrained Implementation of an Educational Microprocessor
Bachelor Thesis
|
|
|
|
 
|
[Goka21]
G. Gokaj
Analysis of a Tableau-based Decision Procedure for CTL*
Bachelor Thesis
|
|
|
|
 
|
[Hack21]
A. Hackenberg
Survey of Open Source Processor Implementations
|
|
|
|
 
|
[Herz21]
M. Herzog
FPGAs in teaching: Applications and Methods
|
|
|
|
 
|
[Kock21]
F. Kockelke
An Overview of Functional Reactive Programming
|
|
|
|
 
|
[Nava21]
R.F. Navarro
The Role of Computer Science in Combating COVID-19
|
|
|
|
 
|
[RBSY21]
O. Rafique and Y. Bai and K. Schneider and G. Yan
Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO Patterns
Euromicro Conference on Digital System Design (DSD)
|
|
|
|
 
|
[RBSY21a]
O. Rafique and Y. Bai and K. Schneider and G. Yan
Synthesis of Heterogeneous Dataflow Models from Synchronous Specifications
Computers, Software, and Applications Conference (COMPSAC)
|
|
|
|
 
|
[RaBS21]
O. Rafique and Y. Bai and K. Schneider
Case Study: Smart Building Automation System -- (Detailed Evaluation Report)
Technical Report
|
|
|
|
 
|
[RaSc21]
O. Rafique and K. Schneider
Integrating Kahn Process Networks as a Model of Computation in an Extendable Model-based Design Framework
International Conference on Model Driven Engineering and Software Development (MODELSWARD)
|
|
|
|
 
|
[Rafi21]
O. Rafique
Embedded Software Synthesis using Heterogeneous Dataflow Models
PhD Thesis
|
|
|
|
 
|
[Sale21]
A. Saleem
Steuerwerkssynthese für Datenflussprogramme
Bachelor Thesis
|
|
|
|
 
|
[Schn21a]
K. Schneider
Translating Structured Sequential Programs to Dataflow Graphs
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[Schn21b]
K. Schneider
Translating Structured Sequential Programs to Dataflow Graphs
Presentation
|
|
|
|
 
|
[Schn21c]
A. Schneiders
A Comparison of Exposed Datapath and Conventional Processor Architectures
Master Thesis
|
|
|
|
 
|
[Schr21]
E. Schreiner
CNN Beschleuniger
|
|
|
|
 
|
[Stei21]
M. Stein
Optimizing Overhead in Compilation for SCAD Architectures
Master Thesis
|
|
|
|
 
|
[Stoc21]
J. Stock
Konfigurationsmanagement mit fachlichen Nutzern als Zielgruppe für ein technisch komplexes System
Bachelor Thesis
|
|
|
|
 
|
[Stol21]
A. Stoll
A Survey of Forecasting Techniques for COVID-19
|
|
|
|
 
|
[Suik21]
M. Suiker
The SACRES Project: Distributed and Modular Code Generation
|
|
|
|
 
|
[WeSc21]
M.C. Werner and K. Schneider
Translation of Continuous Function Charts to Imperative Synchronous Quartz Programs
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[Bhag20]
A. Bhagyanath
Code Generation for Synchronous Control Asynchronous Dataflow Architectures
PhD Thesis
|
|
|
|
 
|
[DaSc20]
M. Dahlem and K. Schneider
Compiling synchronous languages to optimal move code for exposed datapath architectures
International Workshop on Software and Compilers for Embedded Systems (SCOPES)
|
|
|
|
 
|
[Drew20]
M. Drewniok
Programmtransformation zur Vereinfachung des Kontrollflusses
Bachelor Thesis
|
|
|
|
 
|
[Drew20a]
M. Drewniok
Programmtransformation zur Vereinfachung des Kontrollflusses
Presentation
|
|
|
|
 
|
[FGBK20]
J. Froemmer and Y. Gowayed and N. Bannow and W. Kunz and C. Grimm and K. Schneider
Area Estimation Framework for Digital Hardware Design Using Machine Learning
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[Haid20]
S.M. Haider
Evaluating Scheduling Strategies for Executing Neural Networks on OpenCL Platforms
Master Thesis
|
|
|
|
 
|
[Haid20a]
S.M. Haider
Evaluating Scheduling Strategies for Executing Neural Networks on OpenCL Platforms
Presentation
|
|
|
|
 
|
[Heil20]
P. Heiler
Seminar: Live-Verification while Programming: Dafny
|
|
|
|
 
|
[Heil20a]
P. Heiler
Seminar: Live-Verification while Programming: Dafny
Presentation
|
|
|
|
 
|
[Hell20]
S. Heller
Seminar: On Security Features in Commercial Processors
|
|
|
|
 
|
[Hell20a]
S. Heller
Seminar: On Security Features in Commercial Processors
Presentation
|
|
|
|
 
|
[KoHS20]
M. Köhler and F. Hasselwander and K. Schneider
Properties of Invariants and Induction Lemmata
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[Lill20]
M. Lill
Comparing SSA Code Transformations in Compilers
Bachelor Thesis
|
|
|
|
 
|
[Luet20]
A. Lütke-Bordewick
Seminar: A Study on the Development of IoT Systems
|
|
|
|
 
|
[Luet20a]
A. Lütke-Bordewick
Seminar: A Study on the Development of IoT Systems
Presentation
|
|
|
|
 
|
[Pfaf20]
A. Pfaff
Seminar: A study of AEGIS and MI6 Secure Processor Architectures
|
|
|
|
 
|
[Pfaf20a]
A. Pfaff
Seminar: A study of AEGIS and MI6 Secure Processor Architectures
Presentation
|
|
|
|
 
|
[RaSc20]
O. Rafique and K. Schneider
Employing OpenCL as a Standard Hardware Abstraction in a Distributed Embedded System: A Case Study
Conference on Cyber-Physical Systems and Internet-of-Things
|
|
|
|
 
|
[RaSc20a]
O. Rafique and K. Schneider
Employing OpenCL as a Standard Hardware Abstraction in a Distributed Embedded System: A Case Study
Presentation
|
|
|
|
 
|
[RaSc20b]
O. Rafique and K. Schneider
SHeD: A Framework for Automatic Software Synthesis of Heterogeneous Dataflow Process Networks
Euromicro Conference on Digital System Design (DSD)
|
|
|
|
 
|
[RaSc20c]
O. Rafique and K. Schneider
SHeD: A Framework for Automatic Software Synthesis of Heterogeneous Dataflow Process Networks
Presentation
|
|
|
|
 
|
[Rama20]
P.K. Ramachandran
Verification of SysML Models using Hybrid-Testbeds with Model-in-the-Loop Simulations
Master Thesis
|
|
|
|
 
|
[Subr20]
S.N. Subramanya
An Evaluation of WebAssembly on Edge Devices for IoT
Master Thesis
|
|
|
|
 
|
[Tiss20]
S. Tissen
Entwicklung eines Machine-Learning Modells zur Auswertung von Überlebensdaten und Bereitstellung als Web-Service
Bachelor Thesis
|
|
|
|
 
|
[WeSc20]
M.C. Werner and K. Schneider
Reengineering Programmable Logic Controllers Using Synchronous Programming Languages
Forum on Specification and Design Languages (FDL)
|
|
|
|
 
|
[Zeun20]
J. Zeunert
Seminar: Spectre and Meltdown -- A tamed ghost?
|
|
|
|
 
|
[Zeun20a]
J. Zeunert
Seminar: Spectre and Meltdown -- A tamed ghost?
Presentation
|
|
|
|
 
|
[AnKL19]
M. Anders and S. Kwasigroch and M. Lederer
Applied Verification Tasks
Project Thesis
|
|
|
|
 
|
[AnSc19]
M. Anders and K. Schneider
A Formal Semantics of Exposed Datapath Architectures with Buffered Processing Units
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[AnSc19a]
M. Anders and K. Schneider
A Formal Semantics of Exposed Datapath Architectures with Buffered Processing Units
Presentation
|
|
|
|
 
|
[DeST19]
P. Derler and K. Schneider and J.-P. Talpin
Guest Editorial: Special Issue of ACM TECS on the ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017)
ACM Transactions on Embedded Computing Systems (TECS)
|
|
|
|
 
|
[Desh19]
P.D. Deshmukh
Verification of AUTOSAR Basis Software
Master Thesis
|
|
|
|
 
|
[Ego19]
L. Ego
Memory Synchronization Techniques
|
|
|
|
 
|
[Ego19a]
L. Ego
Memory Synchronization Techniques
Presentation
|
|
|
|
 
|
[FBAG19]
J. Frömmer and N. Bannow and A. Aue and C. Grimm and K. Schneider
Model-Based Configuration of a Coarse-Grained Reconfigurable Architecture
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[FBAG19a]
J. Froemmer and N. Bannow and A. Aue and C. Grimm and K. Schneider
Flexible Data Flow Architecture for Embedded Hardware Accelerators
International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP)
|
|
|
|
 
|
[GrSZ19]
Ch. Grimm and K. Schneider and C. Zivkovich
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[Haid19]
S.M. Haider
Synthesis Framework for Executing Neural Networks on Heterogeneous Platforms
Master Thesis
|
|
|
|
 
|
[Harc19]
A. Harchandani
How to Refine Support Experience Using Machine Learning
Master Thesis
|
|
|
|
 
|
[Hass19]
F. Hasselwander
Lemma Generation for Induction-based Proof Rules
Master Thesis
|
|
|
|
 
|
[Jain19]
T. Jain
Nonblocking On-Chip Interconnection Networks
PhD Thesis
|
|
|
|
 
|
[KoSc19]
M. Köhler and K. Schneider
Inductive Proof Rules Beyond Safety Properties
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[Kreb19]
F. Krebs
A Translation Framework from RVC-CAL Dataflow Programs to OpenCL/SYCL based Implementations
Master Thesis
|
|
|
|
 
|
[Kwas19]
S. Kwasigroch
Seminar: The Current State of Property Directed Reachability
|
|
|
|
 
|
[Kwas19a]
S. Kwasigroch
Seminar: The Current State of Property Directed Reachability
Presentation
|
|
|
|
 
|
[Lede19]
M. Lederer
Causal Correctness as a Safety Property
Bachelor Thesis
|
|
|
|
 
|
[Maia19]
E.M. Lemos Maia
(RO)BDD: History and Importance
|
|
|
|
 
|
[Maia19a]
E.M. Lemos Maia
(RO)BDD: History and Importance
Presentation
|
|
|
|
 
|
[Moha19]
M. Mohamed
SIMULINK to DLL (for TSIM Plugin)
Project Thesis
|
|
|
|
 
|
[Mukh19]
P.S. Mukherjee
Data-driven Control with Machine Learning for Optimization of a Cement Mill
Master Thesis
|
|
|
|
 
|
[Neuh19]
Y. Neuhard
A Comparative Study on Existing Dataflow-oriented Frameworks
|
|
|
|
 
|
[Neuh19a]
Y. Neuhard
A Comparative Study on Existing Dataflow-oriented Frameworks
Presentation
|
|
|
|
 
|
[Pete19]
A.K. Peters
Intuitionistic Logic: A View of its Evolution
|
|
|
|
 
|
[Pete19a]
A.K. Peters
Intuitionistic Logic: A View of its Evolution
Presentation
|
|
|
|
 
|
[RaKS19]
O. Rafique and F. Krebs and K. Schneider
Generating Efficient Parallel Code from the RVC-CAL Dataflow Language
Euromicro Conference on Digital System Design (DSD)
|
|
|
|
 
|
[RaKS19a]
O. Rafique and F. Krebs and K. Schneider
Generating Efficient Parallel Code from the RVC-CAL Dataflow Language
Presentation
|
|
|
|
 
|
[RaSc19]
O. Rafique and K. Schneider
Evaluating OpenCL as a Standard Hardware Abstraction for a Model-based Synthesis Framework: A Case Study
International Conference on Model Driven Engineering and Software Development (MODELSWARD)
|
|
|
|
 
|
[RaSc19a]
O. Rafique and K. Schneider
Automatic Software Synthesis of Static and Dynamic Dataflow Process Networks
International Workshop on Interplay of Model-Driven and Component-Based Software Engineering (ModComp)
|
|
|
|
 
|
[RaSc19b]
O. Rafique and K. Schneider
Automatic Software Synthesis of Static and Dynamic Dataflow Process Networks
Presentation
|
|
|
|
 
|
[Schn19]
A. Schneiders
Software and Formal Verification in Avionics
|
|
|
|
 
|
[Schn19a]
A. Schneiders
Software and Formal Verification in Avionics
Presentation
|
|
|
|
 
|
[Scho19]
A. Schönitz
Speculative Execution in Data Flow Processors
|
|
|
|
 
|
[Scho19a]
A. Schönitz
Speculative Execution in Data Flow Processors
Presentation
|
|
|
|
 
|
[Senf19]
M. Senftleben
Modelling Memory Consistency Models for Formal Verification
PhD Thesis
|
|
|
|
 
|
[Thei19]
D. Theis
Restrukturierung der API und Serverkomponente eines mobilen Spiels zur Optimierung der Sicherheit
Bachelor Thesis
|
|
|
|
 
|
[Tiss19]
S. Tissen
Weak Memory Semantics
|
|
|
|
 
|
[Tiss19a]
S. Tissen
Weak Memory Semantics
Presentation
|
|
|
|
 
|
[AnBS18]
M. Anders and A. Bhagyanath and K. Schneider
On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[AnBS18a]
M. Anders and A. Bhagyanath and K. Schneider
On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units
Presentation
|
|
|
|
 
|
[Ande18]
M. Anders
Foundations for Verifiable Reactive Systems on Exposed Datapath Architectures with Buffered Processing Units
Project Thesis
|
|
|
|
 
|
[Ande18a]
M. Anders
Foundations for Verifiable Reactive Systems on Exposed Datapath Architectures with Buffered Processing Units
Presentation
|
|
|
|
 
|
[Beja18]
S. Bejai
Compilation Techniques for Increasing Instruction-level Parallelism for the SCAD Machine
|
|
|
|
 
|
[Beja18a]
S. Bejai
Compilation Techniques for Increasing Instruction-level Parallelism for the SCAD Machine
Presentation
|
|
|
|
 
|
[Betz18]
A. Betz
A survey on OpenCL-based design flows for executing DPNs
|
|
|
|
 
|
[Betz18a]
A. Betz
A survey on OpenCL-based design flows for executing DPNs
Presentation
|
|
|
|
 
|
[Bhat18]
S.N. Bhat
Robustness Assessment of Linux by Simulation-Based Physical Fault Injection in System Calls
Master Thesis
|
|
|
|
 
|
[Bone18]
Y. Bonenberger
Ordering events in distributed systems: A review
|
|
|
|
 
|
[Bone18a]
Y. Bonenberger
Ordering events in distributed systems: A review
Presentation
|
|
|
|
 
|
[Bonk18]
J. Bonkile
Development Tools Tailored for Serverless Cloud Computing
Master Thesis
|
|
|
|
 
|
[Buss18]
L. Busser
Evaluating Learning Algorithms for Regular Expressions
Bachelor Thesis
|
|
|
|
 
|
[DaBS18]
M. Dahlem and A. Bhagyanath and K. Schneider
Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP
Technical Report
|
|
|
|
 
|
[DaBS18b]
M. Dahlem and A. Bhagyanath and K. Schneider
Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP
Theory and Practice of Logic Programming (TPLP)
|
|
|
|
 
|
[Das18a]
T. Das
Classification of Warranty Claim Data using Supervised Machine Learning Algorithm SVM (Support Vector Machine)
Master Thesis
|
|
|
|
 
|
[Dsou18]
E.A. Dsouza
Optical Communication in High Voltage Battery Systems
Master Thesis
|
|
|
|
 
|
[Dsou18a]
E.A. Dsouza
Optical Communication in High Voltage Battery Systems
Presentation
|
|
|
|
 
|
[Geor18]
G. Georgopoulos
Operational Semantics of Memory System Implementations
Master Thesis
|
|
|
|
 
|
[Hubr18]
J. Hubrich
Cracking Enigma, a (short) Summary of the past
|
|
|
|
 
|
[Hubr18a]
J. Hubrich
Cracking Enigma, a (short) Summary of the past
Presentation
|
|
|
|
 
|
[JaSc18]
T. Jain and K. Schneider
The Half Cleaner Lemma: Constructing Efficient Interconnection Networks from Sorting Networks
Parallel Processing Letters
|
|
|
|
 
|
[JaSc18a]
T. Jain and K. Schneider
Routing Partial Permutations in General Interconnection Networks based on Radix Sorting
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[JaSc18b]
T. Jain and K. Schneider
Routing Partial Permutations in General Interconnection Networks based on Radix Sorting
Presentation
|
|
|
|
 
|
[JaSc18c]
T. Jain and K. Schneider
Routing Partial Permutations in Interconnection Networks based on Radix Sorting
International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
|
|
|
|
 
|
[JaSc18d]
T. Jain and K. Schneider
Routing Partial Permutations in Interconnection Networks based on Radix Sorting
Presentation
|
|
|
|
 
|
[JaSc18e]
T. Jain and K. Schneider
A Recursive Concentrator Circuit and its Application as a Building Block of an Interconnection Network
|
|
|
|
 
|
[JaSc18f]
T. Jain and K. Schneider
Optimal Self-Routing Split Modules for Radix-based Interconnection Networks
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[JaSc18g]
T. Jain and K. Schneider
Optimal Self-Routing Split Modules for Radix-based Interconnection Networks
Presentation
|
|
|
|
 
|
[Meck18]
D. Meckel
Fundamentals of Robotics Verification
|
|
|
|
 
|
[Meck18a]
D. Meckel
Fundamentals of Robotics Verification
Presentation
|
|
|
|
 
|
[Mohe18]
S. Mohebbi
The history of P vs. NP
|
|
|
|
 
|
[Mohe18a]
S. Mohebbi
The history of P vs. NP
Presentation
|
|
|
|
 
|
[Muel18]
P. Müller
Control flow and data flow in processors
|
|
|
|
 
|
[Muel18a]
P. Müller
Control flow and data flow in processors
Presentation
|
|
|
|
 
|
[Muen18]
K. Münch
Lazy Grounding und seine Mö̈glichkeiten
|
|
|
|
 
|
[Muen18a]
K. Münch
Lazy Grounding und seine Mö̈glichkeiten
Presentation
|
|
|
|
 
|
[RaSc18]
O. Rafique and K. Schneider
A Model-based Synthesis Framework for the Execution of Dynamic Dataflow Actors
International Conference on Internet of Things Embedded Systems and Communications (IINTEC)
|
|
|
|
 
|
[RaSc18a]
O. Rafique and K. Schneider
A Model-based Synthesis Framework for the Execution of Dynamic Dataflow Actors
Presentation
|
|
|
|
 
|
[Rohr18]
N. Rohr
GOTO Statement: A Balanced View
|
|
|
|
 
|
[Rohr18a]
N. Rohr
GOTO Statement: A Balanced View
Presentation
|
|
|
|
 
|
[ScDa18]
K. Schneider and M. Dahlem
Are Synchronous Programs Logic Programs?
|
|
|
|
 
|
[ScDa18a]
K. Schneider and M. Dahlem
Are Synchronous Programs Logic Programs?
Presentation
|
|
|
|
 
|
[Schn18]
A. Schneiders
Using Static-Single-Information-Form for SCAD Code Generation
Bachelor Thesis
|
|
|
|
 
|
[Schu18]
S. Schumb
Evaluating Interconnection Networks for Exposed Datapath Architectures
Master Thesis
|
|
|
|
 
|
[SeSc18]
M. Senftleben and K. Schneider
Operational Characterization of Weak Memory Consistency Models
International Conference on Architecture of Computing Systems (ARCS)
|
|
|
|
 
|
[SeSc18a]
M. Senftleben and K. Schneider
Using Temporal Logics for Specifying Weak Memory Consistency Models
International Journal of Critical Computer-Based Systems (IJCCBS)
|
|
|
|
 
|
[Ande17]
M. Anders
Complexity Analysis of Code Generation for the SCAD Machine
Bachelor Thesis
|
|
|
|
 
|
[Basa17]
S.R. Basavaraju
Application-specific Configuration of Exposed Datapath Architectures
Master Thesis
|
|
|
|
 
|
[BhSc17]
A. Bhagyanath and K. Schneider
Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[BhSc17a]
A. Bhagyanath and K. Schneider
Exploring different execution paradigms in exposed datapath architectures with buffered processing units
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
|
|
|
|
 
|
[BhSc17b]
A. Bhagyanath and K. Schneider
Exploring Different Execution Paradigms in Exposed Datapath Architectures with Buffered Processing Units
Presentation
|
|
|
|
 
|
[BhSc17c]
A. Bhagyanath and K. Schneider
Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units
Presentation
|
|
|
|
 
|
[DJSG17]
M. Dahlem and T. Jain and K. Schneider and M. Gillmann
Automatic Synthesis of Optimal-Size Concentrators by Answer Set Programming
Logic Programming and Nonmonotonic Reasoning (LPNMR)
|
|
|
|
 
|
[Grue17]
E. Grüner
Systematic Testing and Stateless Model Checking
|
|
|
|
 
|
[Haif17]
F. Haifani
Antichain Optimization using Simulation Relations for Context-Free Games
Master Thesis
|
|
|
|
 
|
[JaSJ17]
T. Jain and K. Schneider and A. Jain
An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip
Network on Chip Architectures (NoCArc)
|
|
|
|
 
|
[JaSJ17a]
T. Jain and K. Schneider and A. Jain
An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip
Presentation
|
|
|
|
 
|
[JaSJ17b]
T. Jain and K. Schneider and A. Jain
Deriving Concentrators from Binary Sorters Using Half Cleaners
Reconfigurable Computing and FPGAs (ReConFig)
|
|
|
|
 
|
[JaSJ17c]
T. Jain and K. Schneider and A. Jain
Deriving Concentrators from Binary Sorters Using Half Cleaners
|
|
|
|
 
|
[JaSW17]
T. Jain and K. Schneider and F. Walk
Out-of-Order Execution of Buffered Function Units in Exposed Data Path Architectures
Reconfigurable Architectures Workshop (RAW)
|
|
|
|
 
|
[JaSW17a]
T. Jain and K. Schneider and F. Walk
Out-of-Order Execution of Buffered Function Units in Exposed Data Path Architectures
Presentation
|
|
|
|
 
|
[Jede17]
E. Jedermann
Application-specific Computing Features in Processors
|
|
|
|
 
|
[Kann17]
S. Kannoth
Synchronous Modelling and Formal Verification of Train Command Management Systems
Master Thesis
|
|
|
|
 
|
[Koen17]
M. Koenig
Complexity Analysis of Register Allocation
|
|
|
|
 
|
[Koen17a]
M. Koenig
Komplexitätsanalyse der Speicherallokation
Presentation
|
|
|
|
 
|
[Kreb17]
F. Krebs
Timing Predictability of Processors
|
|
|
|
 
|
[Kreb17a]
F. Krebs
Timing Predictability of Processors
Presentation
|
|
|
|
 
|
[Kwas17]
S. Kwasigroch
Execution Paradigms in Dataflow Processors
|
|
|
|
 
|
[LeSc17]
A. Legay and K. Schneider
Message from the ACSD 2017 Program Chairs
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[Leon17]
V. Leonhardt
Hoare Calculus for SIMT Programms
|
|
|
|
 
|
[Leon17a]
V. Leonhardt
Hoare Calculus for SIMT Programs
Presentation
|
|
|
|
 
|
[Li17]
X. Li
Induction-based Verification of Synchronous and Hybrid Programs
PhD Thesis
|
|
|
|
 
|
[Neum17]
E. Neumann
Algorithms for Context-free Games: A Comparison of Saturation, Guess and Check, and Summarization
Master Thesis
|
|
|
|
 
|
[Roob17]
J. Roob
OpenCL Implementation of Exposed Data Path Architectures as General Purpose Accelerators
Master Thesis
|
|
|
|
 
|
[ScBr17]
K. Schneider and J. Brandt
Quartz: A Synchronous Language for Model-based Design of Reactive Embedded Systems
|
|
|
|
 
|
[Schm17a]
F. Schmidt
Time Predictable Computer Architecture
Presentation
|
|
|
|
 
|
[Schm17b]
F. Schmidt
Time Predictable Computer Architectures
|
|
|
|
 
|
[Stat17]
M. Stather
Entwicklung einer Kommunikationskomponente mit Sensor-/Aktorinterface auf einem FPGA für das Finroc-Projekt
Bachelor Thesis
|
|
|
|
 
|
[Stut17]
F.M. Stutz
Operations on a Symbolic Domain for Synthesis
Bachelor Thesis
|
|
|
|
 
|
[TaDS17]
J.-P. Talpin and P. Derler and K. Schneider
Message from the Chairs
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[Wend17]
J. Wendel
A selective study on model-based design frameworks
|
|
|
|
 
|
[Wend17a]
J. Wendel
A Selective Study on Model-based Design Frameworks
Presentation
|
|
|
|
 
|
[Wolf17]
K. Wolff
Code Generation for Dataflow Processors
|
|
|
|
 
|
[Zaid17]
S. Zaidi
Performance of OpenCL in Multicore Processors
|
|
|
|
 
|
[Bai16]
Y. Bai
Model-based Design of Embedded Systems by Desynchronization
PhD Thesis
|
|
|
|
 
|
[BhJS16]
A. Bhagyanath and T. Jain and K. Schneider
Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) Architectures
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[BhJS16a]
A. Bhagyanath and T. Jain and K. Schneider
Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) Architectures
Presentation
|
|
|
|
 
|
[BhSc16]
A. Bhagyanath and K. Schneider
Optimal Compilation for Exposed Datapath Architectures with Buffered Processing Units by SAT Solvers
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[BhSc16a]
A. Bhagyanath and K. Schneider
Optimal Compilation for Exposed Datapath Architectures with Buffered Processing Units by SAT Solvers
Presentation
|
|
|
|
 
|
[Buss16]
L. Busser
Inference of regular expressions/grammars for given data entities
|
|
|
|
 
|
[Dein16]
D. Deiniger
Application of Factored Representations from Probabilistic Graphical Models to Probabilistic Verification
Master Thesis
|
|
|
|
 
|
[Desh16]
P.D. Deshmukh
Evaluation and comparison of inter-processor communication techniques in model-based design flows/tools
|
|
|
|
 
|
[Geor16]
G. Georgopoulos
Memory Consistency Models of Modern CPUs
|
|
|
|
 
|
[Geor16a]
G. Georgopoulos
Memory Consistency Models of Modern CPUs
Presentation
|
|
|
|
 
|
[Harm16]
C. Harms
Evaluation of FPGA-based Implementations of Interconnection Networks
Master Thesis
|
|
|
|
 
|
[Heer16]
M. Heer
Verification Condition Generation for Hybrid Systems described by Synchronous Languages
Master Thesis
|
|
|
|
 
|
[Herr16]
F. Herrmann
State of the Art in Temporal Logic Verification
|
|
|
|
 
|
[Herr16a]
F. Herrmann
State of the Art in Temporal Logic Verification
Presentation
|
|
|
|
 
|
[Huse16]
J. Husemann
A Study of Queue Machines
|
|
|
|
 
|
[JaSB16]
T. Jain and K. Schneider and A. Bhagyanath
The Selector-Tree Network: A New Self-Routing and Nonblocking Interconnection Network
International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
|
|
|
|
 
|
[JaSB16a]
T. Jain and K. Schneider and A. Bhagyanath
The Selector-Tree Network: A New Self-Routing and Nonblocking Interconnection Network
Presentation
|
|
|
|
 
|
[JaSc16]
T. Jain and K. Schneider
Verifying the Concentration Property of Permutation Networks by BDDs
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[JaSc16a]
T. Jain and K. Schneider
Verifying the Concentration Property of Permutation Networks by BDDs
Presentation
|
|
|
|
 
|
[John16]
M.R. John
Static Instruction Scheduling for Transport Triggered Architectures
Master Thesis
|
|
|
|
 
|
[Kabo16]
A. Kabouteh
Formal Method Based Analysis of an Ophthalmic Surgical Robot Considering Hard Real-Time Constraints
Master Thesis
|
|
|
|
 
|
[Kann16]
S. Kannoth
A Survey of Real-Time Interconnects
|
|
|
|
 
|
[Krem16]
M. Kremer
Worst Case Reaction Time (WCRT) Analysis Techniques for Synchronous Programs
|
|
|
|
 
|
[LiSc16a]
X. Li and K. Schneider
Control-flow Guided Clause Generation for Property Directed Reachability
High-Level Design Validation and Test Workshop (HLDVT)
|
|
|
|
 
|
[LiSc16b]
X. Li and K. Schneider
Control-flow Guided Clause Generation for Property Directed Reachability
Presentation
|
|
|
|
 
|
[LiSc16c]
X. Li and K. Schneider
Control-flow Guided Property Directed Reachability for Synchronous Programs
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[LiSc16d]
X. Li and K. Schneider
Control-flow Guided Property Directed Reachability for Synchronous Programs
Presentation
|
|
|
|
 
|
[Pand16]
G. Pandit
Compilation Techniques for Reactive Systems
|
|
|
|
 
|
[RBLS16]
T. Ropertz and K. Berns and X. Li and K. Schneider
Verification of Behavior-Based Control Systems in their Physical Environment
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[RBLS16a]
T. Ropertz and K. Berns and X. Li and K. Schneider
Verification of Behavior-Based Control Systems in their Physical Environment
Presentation
|
|
|
|
 
|
[RaSc16]
O. Rafique and K. Schneider
Introducing MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded Systems
International Workshop on Software and Compilers for Embedded Systems (SCOPES)
|
|
|
|
 
|
[RaSc16a]
O. Rafique and K. Schneider
Towards the Standardization of Plug-and-Play Devices for Model-Based Designs of Embedded Systems
Symposium on Industrial Embedded Systems (SIES)
|
|
|
|
 
|
[RaSc16b]
O. Rafique and K. Schneider
Introducing MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded Systems
Presentation
|
|
|
|
 
|
[RaSc16c]
O. Rafique and K. Schneider
MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded Systems
Presentation
|
|
|
|
 
|
[Rao16]
A. Rao
Implementation of a Software Emulator to recreate I2C Sensor Communication
Master Thesis
|
|
|
|
 
|
[RoSF16]
A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira
Semantics in space systems architectures
Innovations in Systems and Software Engineering -- A NASA Journal
|
|
|
|
 
|
[Schu16]
S. Schumb
A Survey of Reactive Processor Architectures
|
|
|
|
 
|
[Schu16a]
S. Schumb
A Survey of Reactive Processor Architectures
Presentation
|
|
|
|
 
|
[SeSc16]
M. Senftleben and K. Schneider
Specifying Weak Memory Consistency with Temporal Logic
Verification and Evaluation of Computer and Communication Systems (VECoS)
|
|
|
|
 
|
[SeSc16a]
M. Senftleben and K. Schneider
Specifying Weak Memory Consistency with Temporal Logic
Presentation
|
|
|
|
 
|
[TaLS16]
J.P. Talpin and E. Leonard and K. Schneider
Welcome Message from the Chairs
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[Walk16a]
F. Walk
Out-of-Order Execution Within Functional Units of the SCAD Architecture
Master Thesis
|
|
|
|
 
|
[Ashr15]
K. Ashraf
HW/SW Co-design and Implementation of a Fountain Code for an FPGA System-on-Chip
Master Thesis
|
|
|
|
 
|
[BaSc15]
D. Baudisch and K. Schneider
Evaluation of Speculation in Out-Of-Order Execution of Synchronous Data-Flow Networks
International Journal of Parallel Programming (IJPP)
|
|
|
|
 
|
[Basa15]
S.R. Basavaraju
WCET-centric Scratchpad Memory Allocation
|
|
|
|
 
|
[Basa15a]
S.R. Basavaraju
WCET-centric Scratchpad Memory Allocation
Presentation
|
|
|
|
 
|
[Betz15]
A. Betz
x86 Memory Consistency
|
|
|
|
 
|
[BhJS15]
A. Bhagyanath and T. Jain and K. Schneider
A Time-Predictable Model of Computation
Real-Time Systems Symposium (RTSS)
|
|
|
|
 
|
[BhJS15a]
A. Bhagyanath and T. Jain and K. Schneider
A Time-Predictable Model of Computation
Presentation
|
|
|
|
 
|
[BhSS15]
N. Bhardwaj and M. Senftleben and K. Schneider
Abacus - A Processor Family for Education
Workshop on Embedded and Cyber-Physical Systems Education (WESE)
|
|
|
|
 
|
[Bich15]
F. Bichued
Verification of Microprocessors
Master Thesis
|
|
|
|
 
|
[Blat15]
D. Blatner
Automatisierte Transformationen von Petri-Netzen zur detaillierten Ablaufkontrolle in verteilten Laufzeitsystemen
Master Thesis
|
|
|
|
 
|
[Eswa15]
A. Eswarappa
AUTOSAR
|
|
|
|
 
|
[FMSS15]
F. Furbach and R. Meyer and K. Schneider and M. Senftleben
Memory-Model-aware Testing -- A Unified Complexity Analysis
Transactions on Embedded Computing Systems (TECS)
|
|
|
|
 
|
[Faus15]
M. Faust
Dataflow processor architecture implementation survey
|
|
|
|
 
|
[Faus15a]
M. Faust
Dataflow processor architecture implementation survey
Presentation
|
|
|
|
 
|
[Froe15]
J. Frömmer
Hoare Calculi for Parallel Programs
|
|
|
|
 
|
[Garc15]
H. Lázaro García
Using UVM for Mixed-Signal Verification with IGBT Driver Context
Master Thesis
|
|
|
|
 
|
[Grei15]
T. Greiner
The use of weak consistency models in cloud storage
|
|
|
|
 
|
[Harm15]
C. Harms
Branch Prediction in WCET Analysis
|
|
|
|
 
|
[Harm15a]
C. Harms
Branch Prediction in WCET Analysis
Presentation
|
|
|
|
 
|
[Jede15]
E. Jedermann
Exposed Datapath Processor Architecture Implementation Survey
|
|
|
|
 
|
[Jede15a]
E. Jedermann
Exposed Datapath Processor Architecture Implementation Survey
Presentation
|
|
|
|
 
|
[Klip15]
N. Klipphahn
Concurrent Model Checking -- Systematic testing/Stateless Model Checking
|
|
|
|
 
|
[Klip15a]
N. Klipphahn
Concurrent Model Checking -- Systematic testing/Stateless Model Checking
Presentation
|
|
|
|
 
|
[Kolh15]
A. Kolhapurkar
Functional Safety: ISO26262
|
|
|
|
 
|
[Lang15]
D. Langguth
Scratchpad memory vs Caches -- Performance and Predictability Comparison
|
|
|
|
 
|
[Lang15a]
D. Langguth
Scratchpad memory vs Caches -- Performance and Predictability Comparison
Presentation
|
|
|
|
 
|
[LiSc15]
X. Li and K. Schneider
A Counterexample-Guided Approach to Symbolic Simulation of Hybrid Systems
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[LiSc15a]
X. Li and K. Schneider
An SMT-based Approach to analyze Non-Linear Relations of Parameters for Hybrid Systems
Formal Modeling and Verification of Cyber-Physical Systems
|
|
|
|
 
|
[LiSc15b]
X. Li and K. Schneider
Verification Condition Generation for Hybrid Systems
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[LiSc15e]
X. Li and K. Schneider
A Counterexample-Guided Approach to Symbolic Simulation of Hybrid Systems
Presentation
|
|
|
|
 
|
[Nogu15]
C. Pereira Nogueira
Caches in Worst Case Execution Time (WCET) Analysis
|
|
|
|
 
|
[Nogu15a]
C. Pereira Nogueira
Caches in Worst Case Execution Time (WCET) Analysis
Presentation
|
|
|
|
 
|
[Pahl15]
P. Pahlevannejad
Speculative Relaxation of Memory Consistency
|
|
|
|
 
|
[Pahl15a]
P. Pahlevannejad
Speculative Relaxation of Memory Consistency
Presentation
|
|
|
|
 
|
[Schu15]
S. Schumb
Hardware Generation for Transport Triggered Architectures
Bachelor Thesis
|
|
|
|
 
|
[Shaz15]
T. Shazadi
Evaluation of Dataflow Process Networks Mapping on Multi-core Processors
Master Thesis
|
|
|
|
 
|
[Stra15]
J. Stratmann
Implementation and Verification of IEEE-conform Floating-Point Arithmetic
Master Thesis
|
|
|
|
 
|
[Tria15]
A. Triambak
Dynamic Scheduling of Instructions in Transport Triggered Architecture based Processors
Master Thesis
|
|
|
|
 
|
[Zhan15]
H. Zhang
E-Gas Überwachungskonzept
|
|
|
|
 
|
[Adam14]
J. Adamczyk
Automotive Application: Engine Control
|
|
|
|
 
|
[BSBK14]
Y. Bai and K. Schneider and N. Bhardwaj and B. Katti and T. Shazadi
From Clock-Driven to Data-Driven Models
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[BSBK14a]
Y. Bai and K. Schneider and N. Bhardwaj and B. Katti and T. Shazadi
From Clock-Driven to Data-Driven Models
Presentation
|
|
|
|
 
|
[BSBK14b]
Y. Bai and K. Schneider and N. Bhardwaj and B. Katti and T. Shazadi
From Clock-Driven to Data-Driven Models
Presentation
|
|
|
|
 
|
[BaBS14]
D. Baudisch and Y. Bai and K. Schneider
Reducing the Communication of Message-Passing Systems Synthesized from Synchronous Programs
Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)
|
|
|
|
 
|
[BaSc14]
Y. Bai and K. Schneider
Isochronous Networks by Construction
Design, Automation and Test in Europe (DATE)
|
|
|
|
 
|
[BhSS14a]
N. Bhardwaj and M. Senftleben and K. Schneider
Abacus – A Processor Family for Education
Presentation
|
|
|
|
 
|
[BhSc14]
A. Bhagyanath and K. Schneider
TTA as Predictable Architecture for Real-Time Applications
International Conference on Science, Engineering, Research and Management (ICSEMR)
|
|
|
|
 
|
[BhSc14a]
A. Bhagyanath and K. Schneider
TTA as Predictable Architecture for Real-Time Applications
Presentation
|
|
|
|
 
|
[Bill14]
J. Billert
Automotive Operating Systems: OSEK/VDX
|
|
|
|
 
|
[BrSB14]
J. Brandt and K. Schneider and Y. Bai
Passive Code in Synchronous Programs
Transactions on Embedded Computing Systems (TECS)
|
|
|
|
 
|
[Dahl14]
M. Dahlem
Interactive Verification of Synchronous Systems in HOL
Master Thesis
|
|
|
|
 
|
[EdGS14]
S.A. Edwards and A. Girault and K. Schneider
Synchronous Programming (SYNCHRON 2013; Dagstuhl Seminar 13471)
Dagstuhl Reports
|
|
|
|
 
|
[Espe14]
D. Espen
Adaptive Cruise Control
|
|
|
|
 
|
[FMSS14]
F. Furbach and R. Meyer and K. Schneider and M. Senftleben
Memory Model-Aware Testing - A Unified Complexity Analysis
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[FMSS14a]
F. Furbach and R. Meyer and K. Schneider and M. Senftleben
Memory Model-aware Testing -- A Unified Complexity Analysis
Presentation
|
|
|
|
 
|
[GeBS14]
M. Gesell and F. Bichued and K. Schneider
Using Different Representations of Synchronous Systems in SAL
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[GeBS14a]
M. Gesell and F. Bichued and K. Schneider
Using Different Representations of Synchronous Systems in SAL
Presentation
|
|
|
|
 
|
[Gese14]
M. Gesell
Interactive Verification of Synchronous Systems
PhD Thesis
|
|
|
|
 
|
[Heer14]
M. Heer
Assembler Code-Generierung aus synchronen Aktionen
Bachelor Thesis
|
|
|
|
 
|
[Heil14]
P. Heiler
CAN -- Controller Area Network
|
|
|
|
 
|
[Hubr14]
J. Hubrich
Fahrdynamikregelung
|
|
|
|
 
|
[Kaes14]
M. Kaesberger
Fahrzeugdiagnose
|
|
|
|
 
|
[KhBS14]
M. Ammar Ben Khadra and Y. Bai and K. Schneider
Synthesis of Distributed Synchronous Specifications to SysteMoC
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[KhBS14a]
M.A. Ben Khadra and Y. Bai and K. Schneider
High Level Modeling of Elastic Circuits in SystemC
Symposium on Theory of Modeling and Simulation (TMS/DEVS)
|
|
|
|
 
|
[KhBS14b]
M.A. Ben Khadra and Y. Bai and K. Schneider
Synthesis of Distributed Synchronous Specifications to SysteMoC
Presentation
|
|
|
|
 
|
[Kimp14]
M. Kimpel
Automotive Software Modules and Interfaces: ASAM MDX
|
|
|
|
 
|
[Knob14]
J.B. Knobloch
LIN-Bus
|
|
|
|
 
|
[LiSc14]
X. Li and K. Schneider
Interactive Verification of Hybrid Systems
Automated Verification of Critical Systems (AVoCS)
|
|
|
|
 
|
[LiSc14b]
X. Li and K. Schneider
Interactive Verification of Hybrid Systems
Presentation
|
|
|
|
 
|
[Maca14]
M.N. Basurto Macavilca
Endochrony of Distributed Systems
Diploma Thesis
|
|
|
|
 
|
[RSFB14]
A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira and Y. Bai
Using the Base Semantics given by fUML for Verification
Presentation
|
|
|
|
 
|
[Rede14]
M. Reder
Code Generation for Transport Triggered Architecture
Bachelor Thesis
|
|
|
|
 
|
[RoSF14]
A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira
Integrating UML Composite Structures and fUML
International Conference on Current Trends in Theory and Practice of Computer Science (SOFSEM)
|
|
|
|
 
|
[RoSF14a]
A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira
Using the Base Semantics given by fUML for Verification
International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
|
|
|
|
 
|
[RoSF14b]
A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira
Integrating UML Composite Structures and fUML
Presentation
|
|
|
|
 
|
[Rome14]
A. Gerlinger Romero
Hybrid fUML: A Hybrid Synchronous Language
PhD Thesis
|
|
|
|
 
|
[Roob14]
J. Roob
A Hardware Abstraction Layer for Model-based Design of Embedded Systems
Bachelor Thesis
|
|
|
|
 
|
[SCSO14]
K. Schneider and N. Chang and Y. Shin and S. Ozev
International Conference on Computer Design (ICCD)
|
|
|
|
 
|
[ScWi14]
K. Schneider and A. Willenbücher
A New Algorithm for Carry-Free Addition of Binary Signed-Digit Numbers
Field-Programmable Custom Computing Machines (FCCM)
|
|
|
|
 
|
[ScWi14a]
K. Schneider and A. Willenbücher
A New Algorithm for Carry-Free Addition of Binary Signed-Digit Numbers
Presentation
|
|
|
|
 
|
[Schm14b]
F. Schmidt
Automotive Communication Architectures: MOST
|
|
|
|
 
|
[Schn14]
F. Schnicke
ASCET-MD
|
|
|
|
 
|
[TBGS14]
J.-P. Talpin and J. Brandt and M. Gemünde and K. Schneider and S. Shukla
Constructive Polychronous Systems
Science of Computer Programming (SCICO)
|
|
|
|
 
|
[Thie14]
D. Thielsch
Analysis of Concurrency in Synchronous Systems
Master Thesis
|
|
|
|
 
|
[Tria14]
A. Triambak
Timing Anomalies and WCET Analysis
|
|
|
|
 
|
[BGSS13]
J. Brandt and M. Gemünde and K. Schneider and S.K. Shukla and J.-P. Talpin
Embedding Polychrony into Synchrony
IEEE Transactions on Software Engineering (TSE)
|
|
|
|
 
|
[BSCO13]
G. Byrd and K. Schneider and N. Chang and S. Ozev
International Conference on Computer Design (ICCD)
|
|
|
|
 
|
[Baud13]
D. Baudisch
Synthesis of Synchronous Programs to Parallel Software Architectures
PhD Thesis
|
|
|
|
 
|
[Bich13]
F. Bichued
Cyber Physical System Verification with SAL
|
|
|
|
 
|
[Bich13a]
F. Bichued
Cyber Physical System Verification with SAL
Presentation
|
|
|
|
 
|
[Bran13]
J. Brandt
Synchronous Models for Embedded Software
Habilitation Thesis
|
|
|
|
 
|
[Ciol13]
G.A. Ciolacu
Introducing Simulation of Hybrid Systems with the Modelica Tool
|
|
|
|
 
|
[Ciol13a]
G.A. Ciolacu
Introducing Simulation of Hybrid Systems with the Modelica Tool
Presentation
|
|
|
|
 
|
[GeBS13]
M. Gemünde and J. Brandt and K. Schneider
Clock Refinement in Imperative Synchronous Languages
EURASIP Journal on Embedded Systems
|
|
|
|
 
|
[GeLS13]
M. Gesell and X. Li and K. Schneider
Interactive Verification of Cyber-physical Systems
Presentation
|
|
|
|
 
|
[GeMS13]
M. Gesell and A. Morgenstern and K. Schneider
Lifting Verification Results for Preemption Statements
Software Engineering and Formal Methods (SEFM)
|
|
|
|
 
|
[GeMS13a]
M. Gesell and A. Morgenstern and K. Schneider
Lifting Verification Results for Preemption Statements
Presentation
|
|
|
|
 
|
[GeSc13]
M. Gesell and K. Schneider
An Interactive Verification Tool for Synchronous/Reactive Systems
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[GeSc13a]
M. Gesell and K. Schneider
Modular Verification of Synchronous Programs
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[GeSc13b]
M. Gesell and K. Schneider
Modular Verification of Synchronous Programs
Presentation
|
|
|
|
 
|
[GeSc13c]
M. Gesell and K. Schneider
Translating synchronous guarded actions to interleaved guarded actions
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[GeSc13d]
M. Gesell and K. Schneider
Translating Synchronous Guarded Actions to Interleaved Guarded Actions
Presentation
|
|
|
|
 
|
[Gemu13a]
M. Gemünde
Clock Refinement in Imperative Synchronous Programs
PhD Thesis
|
|
|
|
 
|
[Humb13]
Y. Humbert
Umsetzung und Vergleich der Ausführung einer rechenintensiven Echtzeitanwendung mittels OpenMP und CUDA am Beispiel des Beamforming-Algorithmus
Master Thesis
|
|
|
|
 
|
[Khad13]
M.A. Ben Khadra
A Model-based Approach To Sychronous Elastic Systems
Master Thesis
|
|
|
|
 
|
[LiBS13]
X. Li and K. Bauer and K. Schneider
Interactive Verification of Cyber-physical Systems: Interfacing Averest and KeYmaera
International Workshop on Cyber-Physical Systems (IWCPS)
|
|
|
|
 
|
[LiBS13a]
X. Li and K. Bauer and K. Schneider
Interactive Verification of Cyber-physical Systems Interfacing Averest and KeYmaera
Presentation
|
|
|
|
 
|
[MSLG13]
A. Morgenstern and K. Schneider and S. Lamberti and M. Gesell
From LTL to Symbolically Represented Deterministic Automata
Presentation
|
|
|
|
 
|
[MoGS13]
A. Morgenstern and M. Gesell and K. Schneider
Solving Games Using Incremental Induction
Integrated Formal Methods (IFM)
|
|
|
|
 
|
[MoGS13a]
A. Morgenstern and M. Gesell and K. Schneider
Solving Games Using Incremental Induction
Presentation
|
|
|
|
 
|
[RaGS13]
O. Rafique and M. Gesell and K. Schneider
Generating hardware specific code at different abstraction levels using Averest
International Workshop on Software and Compilers for Embedded Systems (SCOPES)
|
|
|
|
 
|
[RaGS13a]
O. Rafique and M. Gesell and K. Schneider
Targeting Different Abstraction Layers by Model-Based Design Methods for Embedded Systems: A Case Study
Real-Time Computing Systems and Applications (RTCSA)
|
|
|
|
 
|
[RaGS13b]
O. Rafique and M. Gesell and K. Schneider
Generating Hardware-Specific Code at Different Abstraction Levels using Averest
Presentation
|
|
|
|
 
|
[RaGS13c]
O. Rafique and M. Gesell and K. Schneider
Learning Various Aspects of a Distributed Real-Time Automotive Embedded System
Workshop on Embedded and Cyber-Physical Systems Education (WESE)
|
|
|
|
 
|
[Rafi13]
O. Rafique
Design, Development, and Integration of a Wireless Communication Unit in ConceptCar
Master Thesis
|
|
|
|
 
|
[RoSF13]
A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira
Synchronous Specialization of Alf for Cyber-Physical Systems
First Open EIT ICT Labs Workshop on Cyber-Physical Systems Engineering
|
|
|
|
 
|
[RoSF13a]
A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira
Towards the Applicability of Alf to Model Cyber-Physical Systems
International Workshop on Cyber-Physical Systems (IWCPS)
|
|
|
|
 
|
[RoSF13b]
A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira
Synchronous Specialization of Alf for Cyber-Physical Systems
Presentation
|
|
|
|
 
|
[RoSF13c]
A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira
Towards the Applicability of Alf to Model Cyber-Physical Systems
Presentation
|
|
|
|
 
|
[Schu13c]
S. Schumb
Cyber Physical System Verification Seminar: Event-B
|
|
|
|
 
|
[Schu13d]
S. Schumb
Cyber Physical System Verification Seminar: Event-B
Presentation
|
|
|
|
 
|
[Senf13]
M. Senftleben
Operational Characterization of Weak Memory Consistency Models
Master Thesis
|
|
|
|
 
|
[TBGS13]
J.-P. Talpin and J. Brandt and M. Gemünde and K. Schneider and S. Shukla
Constructive Polychronous Systems
Logical Foundations of Computer Science (LFCS)
|
|
|
|
 
|
[Walk13]
F. Walk
Parallel Software Generated from Synchronous Programs -- A Performance Evaluation Using a Ray Tracer
Bachelor Thesis
|
|
|
|
 
|
[WiSc13]
A. Willenbücher and K. Schneider
Automatic Hard Block Inference on FPGAs
Euromicro Conference on Digital System Design
|
|
|
|
 
|
[WiSc13a]
A. Willenbücher and K. Schneider
Automatic Hard Block Inference on FPGAs
Presentation
|
|
|
|
 
|
[BGSS12]
J. Brandt and M. Gemünde and K. Schneider and S.K. Shukla and J.-P. Talpin
Representation of Synchronous, Asynchronous, and Polychronous Components by Clocked Guarded Actions
Design Automation for Embedded Systems (DAEM)
|
|
|
|
 
|
[BaBS12]
D. Baudisch and J. Brandt and K. Schneider
Out-Of-Order Execution of Synchronous Data-Flow Networks
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
|
|
|
|
 
|
[BaBS12a]
D. Baudisch and J. Brandt and K. Schneider
Efficient Handling of Arrays in Dataflow Process Networks
International Conference on Embedded Software and Systems (ICESS)
|
|
|
|
 
|
[BaBS12b]
Y. Bai and J. Brandt and K. Schneider
Preservation of LTL Properties in Desynchronized Systems
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[BaBS12c]
Y. Bai and J. Brandt and K. Schneider
Monitoring Distributed Reactive Systems
High Level Design Validation and Test Workshop (HLDVT)
|
|
|
|
 
|
[BaBS12d]
D. Baudisch and J. Brandt and K. Schneider
Out-Of-Order Execution of Synchronous Data-Flow Networks
Presentation
|
|
|
|
 
|
[BaBS12e]
D. Baudisch and J. Brandt and K. Schneider
Efficient Handling of Arrays in Dataflow Process Networks
Presentation
|
|
|
|
 
|
[BaSc12a]
K. Bauer and K. Schneider
Teaching Cyber-Physical Systems: A Programming Approach
Workshop on Embedded and Cyber-Physical Systems Education (WESE)
|
|
|
|
 
|
[BaSc12b]
D. Baudisch and K. Schneider
GPGPU Architectures -- Compiler Techniques and Applications
|
|
|
|
 
|
[Baue12]
K. Bauer
A New Modelling Language for Cyber-physical Systems
PhD Thesis
|
|
|
|
 
|
[Blat12]
D. Blatner
OpenACC and the PGI Compiler
|
|
|
|
 
|
[Blat12a]
D. Blatner
OpenACC and the PGI Compiler
Presentation
|
|
|
|
 
|
[BrSE12]
J. Brandt and K. Schneider and S.A. Edwards
Translating SHIM to Guarded Actions
Technical Report
|
|
|
|
 
|
[BrSc12]
J. Brandt and K. Schneider
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[Eick12]
T. Eickhoff
Program Sketching Using Craig Interpolants
Bachelor Thesis
|
|
|
|
 
|
[GeSc12]
M. Gesell and K. Schneider
A Hoare calculus for the verification of synchronous languages
Programming Languages meets Program Verification (PLPV)
|
|
|
|
 
|
[GeSc12a]
M. Gesell and K. Schneider
Interactive Verification of Synchronous Systems
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[Grae12a]
M. Gräfe
GPU Architektur und Programmiermö̈glichkeiten fü̈r GPGPU-Anwendungen
Presentation
|
|
|
|
 
|
[Grae12b]
M. Gräfe
GPU Architektur und Programmiermö̈glichkeiten fü̈r GPGPU-Anwendungen
|
|
|
|
 
|
[Humb12]
Y. Humbert
Simulation digitaler Schaltungen auf GPUs
|
|
|
|
 
|
[Humb12a]
Y. Humbert
Simulation digitaler Schaltungen auf GPUs
Presentation
|
|
|
|
 
|
[Koel12]
J. Kölsch
Automatische C-to-CUDA Code Generierung
|
|
|
|
 
|
[Koel12a]
J. Kölsch
Automatische C-to-CUDA Code Generierung
Presentation
|
|
|
|
 
|
[Liet12]
B. Lietzow
A Domain Specific Language for the Synthesis of Networked Embedded Systems
Master Thesis
|
|
|
|
 
|
[MoGS12]
A. Morgenstern and M. Gesell and K. Schneider
An Asymptotically Correct Finite Path Semantics for LTL
Logic for Programming, Artificial Intelligence, and Reasoning (LPAR)
|
|
|
|
 
|
[Ratz12]
A. Ratzke
An introduction to the research on Scratchpad memory with focus on performance improvement -- Instruction SPM, SPM on Multicoresystems and SPM on Multitaskingsystems
|
|
|
|
 
|
[Ratz12a]
A. Ratzke
An introduction to the research on Scratchpad memory with focus on performance improvement -- Instruction SPM, SPM on Multicoresystems and SPM on Multitaskingsystems
Presentation
|
|
|
|
 
|
[Roob12]
J. Roob
An Introduction to the Research on Scratchpad Memory: Definition, Hardware, Known Implementations and WCET Optimisation
|
|
|
|
 
|
[Roob12a]
J. Roob
An Introduction to the Research on Scratchpad Memory: Definition, Hardware, Known Implementations and WCET Optimisation
Presentation
|
|
|
|
 
|
[Senf12]
M. Senftleben
Dataflow Programming on GPUs
|
|
|
|
 
|
[Senf12a]
M. Senftleben
Dataflow Programming on GPUs
Presentation
|
|
|
|
 
|
[Stra12]
J. Stratmann
Design and Implementation of a Floating-Point Application Specific Instruction Set Processor
Bachelor Thesis
|
|
|
|
 
|
[TBBS12]
S. Tahar and G. Byrd and P. Bose and K. Schneider
International Conference on Computer Design (ICCD)
|
|
|
|
 
|
[Thie12]
D. Thielsch
Criteria of Endo/Isochrony in Quartz
Bachelor Thesis
|
|
|
|
 
|
[Thie12a]
D. Thielsch
Verifikation auf paralleler Hardware
Presentation
|
|
|
|
 
|
[Thie12b]
D. Thielsch
Verifikation auf paralleler Hardware
|
|
|
|
 
|
[Thul12]
J. Thull
Ein Testkonzept für Efficient XML Interchange (EXI) im Automobilbereich
Master Thesis
|
|
|
|
 
|
[Walk12]
F. Walk
Porting CUDA code to multicore CPUs and other platforms
|
|
|
|
 
|
[Walk12a]
F. Walk
Porting CUDA code to multicore CPUs and other platforms
Presentation
|
|
|
|
 
|
[Will12a]
S. Willenbrock
Speculative Execution of Data Flow Process Networks
Master Thesis
|
|
|
|
 
|
[BGSS11]
J. Brandt and M. Gemünde and K. Schneider and S. Shukla and J.-P. Talpin
Integrating System Descriptions by Clocked Guarded Actions
Forum on Specification and Design Languages (FDL)
|
|
|
|
 
|
[BaBS11]
Y. Bai and J. Brandt and K. Schneider
Data-Flow Analysis of Extended Finite State Machines
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[BaBS11a]
Y. Bai and J. Brandt and K. Schneider
SMT-Based Optimization for Synchronous Programs
Software and Compilers for Embedded Systems (SCOPES)
|
|
|
|
 
|
[BaBS11b]
D. Baudisch and J. Brandt and K. Schneider
Translating Synchronous Systems to Data-Flow Process Networks
Parallel and Distributed Computing, Applications and Technologies (PDCAT)
|
|
|
|
 
|
[BaBS11c]
D. Baudisch and J. Brandt and K. Schneider
Translating Synchronous Systems to Data-Flow Process Networks
Presentation
|
|
|
|
 
|
[BaSc11]
K. Bauer and K. Schneider
Transferring Causality Analysis from Synchronous Programs to Hybrid Programs
International Modelica Conference
|
|
|
|
 
|
[Blat11]
D. Blatner
Out-of-Order Execution of Data-flow Process Networks for Streaming Applications
Bachelor Thesis
|
|
|
|
 
|
[BrSc11]
J. Brandt and K. Schneider
Round Trip to Asynchrony and Synchrony
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[BrSc11a]
J. Brandt and K. Schneider
Separate Translation of Synchronous Programs to Guarded Actions
Technical Report
|
|
|
|
 
|
[GTBS11]
G. Gaydadjiev and S. Tahar and G. Byrd and K. Schneider
International Conference on Computer Design (ICCD)
|
|
|
|
 
|
[GeBS11]
M. Gemünde and J. Brandt and K. Schneider
Schizophrenia and Causality in the Context of Refined Clocks
Forum on Specification and Design Languages (FDL)
|
|
|
|
 
|
[GeBS11a]
M. Gemünde and J. Brandt and K. Schneider
Causality Analysis of Synchronous Programs with Refined Clocks
High Level Design Validation and Test Workshop (HLDVT)
|
|
|
|
 
|
[HGPB11]
K. Heckemann and M. Gesell and T. Pfister and K. Berns and K. Schneider and M. Trapp
Safe Automotive Software
Knowledge-Based and Intelligent Information and Engineering Systems (KES)
|
|
|
|
 
|
[Kolt11]
D. Koltermann
Vektorisierungstechniken zur Nutzung der Multimedia-Extensions
|
|
|
|
 
|
[Kolt11a]
D. Koltermann
Vektorisierungstechniken zur Nutzung der Multimedia-Extensions
Presentation
|
|
|
|
 
|
[MoSc11]
A. Morgenstern and K. Schneider
Synthesis of Parallel Sorting Networks using SAT Solvers
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[MoSc11a]
A. Morgenstern and K. Schneider
A LTL Fragment for $ GR (1)$-Synthesis
International Workshop on Interactions, Games and Protocols (IWIGP)
|
|
|
|
 
|
[MoSc11b]
A. Morgenstern and K. Schneider
Program Sketching via CTL* Model Checking
Model Checking Software (SPIN)
|
|
|
|
 
|
[MoSc11e]
A. Morgenstern and K. Schneider
Synthesis of Sorting Networks using SAT Solvers
Presentation
|
|
|
|
 
|
[MoSc11f]
A. Morgenstern and K. Schneider
Program Sketching via CTL* Model Checking
Presentation
|
|
|
|
 
|
[Nazi11]
R. Nazier
Parallel Programming Models and Hybrid MPI/SMPSs Approach
|
|
|
|
 
|
[Nazi11a]
R. Nazier
Parallel Programming Models and Hybrid MPI/SMPSs Approach
Presentation
|
|
|
|
 
|
[Senf11]
M. Senftleben
Web-based instruction-level simulation of a parameterized dynamic processor
Bachelor Thesis
|
|
|
|
 
|
[Thul11]
J. Thull
Translating OpenMP Programs for Distributed-Memory Systems
|
|
|
|
 
|
[Thul11a]
J. Thull
Translating OpenMP Programs for Distributed-Memory Systems
Presentation
|
|
|
|
 
|
[BELS10]
A. Benveniste and S.A. Edwards and E. Lee and K. Schneider and R. von Hanxleden
SYNCHRON: Abstracts Collection of Dagstuhl Seminar 09481
|
|
|
|
 
|
[BSAS10]
J. Brandt and K. Schneider and S. Ahuja and S.K. Shukla
The Model Checking View to Clock Gating and Operand Isolation
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[BaBS10]
D. Baudisch and J. Brandt and K. Schneider
Multithreaded Code from Synchronous Programs: Extracting Independent Threads for OpenMP
Design, Automation and Test in Europe (DATE)
|
|
|
|
 
|
[BaBS10a]
D. Baudisch and J. Brandt and K. Schneider
Multithreaded Code from Synchronous Programs: Generating Software Pipelines for OpenMP
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[BaBS10b]
D. Baudisch and J. Brandt and K. Schneider
Dependency-Driven Distribution of Synchronous Programs
Distributed and Parallel Embedded Systems (DIPES)
|
|
|
|
 
|
[BaBS10c]
D. Baudisch and J. Brandt and K. Schneider
Multithreaded Code from Synchronous Programs: Extracting Independent Threads for OpenMP
Presentation
|
|
|
|
 
|
[BaBS10d]
D. Baudisch and J. Brandt and K. Schneider
Multithreaded Code from Synchronous Programs: Generating Software Pipelines for OpenMP
Presentation
|
|
|
|
 
|
[BaBS10e]
D. Baudisch and J. Brandt and K. Schneider
Dependency-Driven Distribution of Synchronous Programs
Presentation
|
|
|
|
 
|
[BaGS10]
K. Bauer and R. Gentilini and K. Schneider
A Uniform Approach to Three-Valued Semantics for mu-Calculus on Abstractions of Hybrid Automata
Software Tools for Technology Transfer (STTT)
|
|
|
|
 
|
[BaSc10]
K. Bauer and K. Schneider
From synchronous programs to symbolic representations of hybrid systems
Hybrid Systems: Computation and Control (HSCC)
|
|
|
|
 
|
[BaSc10a]
K. Bauer and K. Schneider
Predicting Events for the Simulation of Hybrid Systems
International Conference on Computer and Information Technology (CIT)
|
|
|
|
 
|
[Bai10]
Y. Bai
Dependency Analysis of Synchronous Programming Languages
Master Thesis
|
|
|
|
 
|
[BrGS10]
J. Brandt and M. Gemünde and K. Schneider
From Synchronous Guarded Actions to SystemC
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[BrSS10]
J. Brandt and K. Schneider and S.K. Shukla
Translating concurrent action oriented specifications to synchronous guarded actions
Languages, Compilers, and Tools for Embedded Systems (LCTES)
|
|
|
|
 
|
[GeBS10]
M. Gemünde and J. Brandt and K. Schneider
Clock Refinement in Imperative Synchronous Languages
SYNCHRON'09: Abstracts Collection of Dagstuhl Seminar 09481
|
|
|
|
 
|
[GeBS10a]
M. Gemünde and J. Brandt and K. Schneider
A Formal Semantics of Clock Refinement in Imperative Synchronous Languages
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[GeBS10b]
M. Gemünde and J. Brandt and K. Schneider
Compilation of Imperative Synchronous Programs with Refined Clocks
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[MoSc10]
A. Morgenstern and K. Schneider
Exploiting the Temporal Logic Hierarchy and the Non-Confluence Property for Efficient LTL Synthesis
Games, Automata, Logics, and Formal Verification (GandALF)
|
|
|
|
 
|
[MoSc10a]
A. Morgenstern and K. Schneider
Exploiting the Temporal Logic Hierarchy and the Non-Confluence Property for Efficient LTL Synthesis
Presentation
|
|
|
|
 
|
[Morg10]
A. Morgenstern
Symbolic Controller Synthesis for LTL Specifications
PhD Thesis
|
|
|
|
 
|
[Rope10]
T. Ropertz
Efficient Execution of Synchronous Guarded Actions using CUDA
Bachelor Thesis
|
|
|
|
 
|
[SJCB10]
K. Schneider and B. Jobstmann and L. Carloni and J. Brandt
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[Will10]
A. Willenbücher
Optimizing Combinational Circuits for FPGAs Using Genetic Programming
Master Thesis
|
|
|
|
 
|
[BaGS09]
D. Baudisch and M. Gesell and K. Schneider
Online Exercise System -- A Web-Based Tool for Administration and Automatic Correction of Exercises
Computer Supported Education (CSEDU)
|
|
|
|
 
|
[BaGS09a]
K. Bauer and R. Gentilini and K. Schneider
Property Driven Three-Valued Model Checking on Hybrid Automata
Workshop on Logic, Language, Information and Computation (WoLLIC)
|
|
|
|
 
|
[BaGS09b]
K. Bauer and R. Gentilini and K. Schneider
A Uniform Approach to Three-Valued Semantics for mu-Calculus on Abstractions of Hybrid Automata
Haifa Verification Conference (HVC)
|
|
|
|
 
|
[BaGS09c]
D. Baudisch and M. Gesell and K. Schneider
Online Exercise System -- A Web-Based Tool for Administration and Automatic Correction of Exercises
Presentation
|
|
|
|
 
|
[BrGS09]
J. Brandt and M. Gemünde and K. Schneider
Desynchronizing Synchronous Programs by Modes
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[BrSW09]
J. Brandt and K. Schneider and A. Willenbücher
Using IP Cores in Synchronous Languages
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[BrSc09]
J. Brandt and K. Schneider
Separate Compilation for Synchronous Programs
Software and Compilers for Embedded Systems (SCOPES)
|
|
|
|
 
|
[BrSc09a]
J. Brandt and K. Schneider
Static Data-Flow Analysis of Synchronous Programs
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[Schn09]
K. Schneider
The Synchronous Programming Language Quartz
Technical Report
|
|
|
|
 
|
[VeTS09]
E. Vecchié and J.-P. Talpin and K. Schneider
Separate Compilation and Execution of Imperative Synchronous Modules
Design, Automation and Test in Europe (DATE)
|
|
|
|
 
|
[BaGS08]
K. Bauer and R. Gentilini and K. Schneider
Approximated Reachability on Hybrid Automata: Falsification meets Certification
Electronic Notes in Theoretical Computer Science (ENTCS)
|
|
|
|
 
|
[Baud08]
D. Baudisch
Synthesis for VLIW Architectures
Diploma Thesis
|
|
|
|
 
|
[Baue08b]
K. Bauer
Algebraic Methods and Abstractions for Automated 3-valued Reasoning on Hybrid Automata
Diploma Thesis
|
|
|
|
 
|
[BrSW08]
J. Brandt and K. Schneider and A. Willenbücher
Hardware Acceleration for Model Checking
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[BrSc08]
J. Brandt and K. Schneider
Embedded Systems: Status and Perspective
|
|
|
|
 
|
[BrSc08a]
J. Brandt and K. Schneider
Formal Reasoning About Causality Analysis
Theorem Proving in Higher Order Logics (TPHOL)
|
|
|
|
 
|
[DyWi08]
S. Dyckmans and A. Willenbücher
Design and Implementation of a Dataflow-Processor for Synchronous Programs
Bachelor Thesis
|
|
|
|
 
|
[EdSc08]
S. Edwards and K. Schneider
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[Gemu08]
M. Gemünde
Evaluation Environment for AUTOSAR-Autocode in Motor Control Units
Diploma Thesis
|
|
|
|
 
|
[Gese08]
M. Gesell
Probabilistic Model Checking of Synchronous Programs
Diploma Thesis
|
|
|
|
 
|
[MoSL08]
A. Morgenstern and K. Schneider and S. Lamberti
Generating Deterministic $\omega$-Automata for most LTL Formulas by the Breakpoint Construction
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[MoSL08b]
A. Morgenstern and K. Schneider and S. Lamberti
Generating Deterministic $\omega$-Automata for most LTL formulas by the Breakpoint Construction
Presentation
|
|
|
|
 
|
[MoSc08]
A. Morgenstern and K. Schneider
From LTL to Symbolically Represented Deterministic Automata
Verification, Model Checking, and Abstract Interpretation (VMCAI)
|
|
|
|
 
|
[MoSc08c]
A. Morgenstern and K. Schneider
From LTL to Symbolically Represented Deterministic Automata
Presentation
|
|
|
|
 
|
[PoSc08]
A. Poetzsch-Heffter and K. Schneider
Workshop on Verification of Adaptive Systems (VerAS)
Electronic Notes in Theoretical Computer Science (ENTCS)
|
|
|
|
 
|
[ScBr08]
K. Schneider and J. Brandt
Performing Causality Analysis by Bounded Model Checking
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[Schm08]
S. Schmitt
Supervisor Synthesis using SAT-Solvers
Diploma Thesis
|
|
|
|
 
|
[Baue07]
K. Bauer
On the Use of Gröbner Bases and Algebraic Methods for the Analysis of Hybrid Automata
Project Thesis
|
|
|
|
 
|
[Baue07a]
K. Bauer
Three-valued $\mu$-Calculus on Hybrid Automata
Diploma Thesis
|
|
|
|
 
|
[BrSc07]
J. Brandt and K. Schneider
Different Kinds of System Descriptions as Synchronous Programs
|
|
|
|
 
|
[BrSc07b]
J. Brandt and K. Schneider
How Different are Esterel and SystemC?
Forum on Specification and Design Languages (FDL)
|
|
|
|
 
|
[Bran07]
J. Brandt
A Layered Approach to Polygon Processing for Safety-Critical Embedded Systems
PhD Thesis
|
|
|
|
 
|
[GeGe07]
M. Gesell and M. Gemünde
Eine Oberfläche zur Simulation synchroner Sprachen
Project Thesis
|
|
|
|
 
|
[GeSD07a]
R. Gentilini and K. Schneider and A. Dreyer
Combining Interval Arithmetic and Three-Valued Temporal Logics for the Verification of Analog Systems
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[GeSD07b]
R. Gentilini and K. Schneider and A. Dreyer
Three-Valued Automated Reasoning on Analog Properties
Great Lakes Symposium on VLSI (GLSVLSI)
|
|
|
|
 
|
[GeSM07]
R. Gentilini and K. Schneider and B. Mishra
Successive Abstractions of Hybrid Automata for Monotonic CTL Model Checking
Logical Foundations of Computer Science (LFCS)
|
|
|
|
 
|
[HoSc07]
J.C. Hoe and K. Schneider
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[MoSc07]
A. Morgenstern and K. Schneider
Synthesizing Deterministic Controllers in Supervisory Control
Informatics in Control, Automation and Robotics (ICINCO)
|
|
|
|
 
|
[PBSS07]
M. Proetzsch and K. Berns and T. Schüle and K. Schneider
Formal Verification of Safety Behaviours of the Outdoor Robot RAVON
Informatics in Control, Automation and Robotics (ICINCO)
|
|
|
|
 
|
[PoSc07]
A. Poetzsch-Heffter and K. Schneider
First DASMOD Workshop on Verification of Adaptive Systems (VerAS)
Technical Report
|
|
|
|
 
|
[ScBr07]
K. Schneider and J. Brandt
Theorem Proving in Higher Order Logics (TPHOL)
|
|
|
|
 
|
[ScBr07a]
K. Schneider and J. Brandt
Theorem Proving in Higher Order Logics and Applications -- Emerging Trends
Technical Report
|
|
|
|
 
|
[ScSc07]
T. Schüle and K. Schneider
Verification of Data Paths Using Unbounded Integers: Automata Strike Back
Haifa Verification Conference (HVC)
|
|
|
|
 
|
[ScSc07a]
T. Schüle and K. Schneider
Bounded Model Checking of Infinite State Systems
Formal Methods in System Design (FMSD)
|
|
|
|
 
|
[Schu07]
T. Schüle
Verification of Infinite State Systems Using Presburger Arithmetic
PhD Thesis
|
|
|
|
 
|
[TuSG07]
T. Türk and K. Schneider and M. Gordon
Model Checking PSL Using HOL and SMV
Haifa Verification Conference (HVC)
|
|
|
|
 
|
[Baud06]
D. Baudisch
Implementierung und Verifikation eines RISC-Prozessors in Averest
Project Thesis
|
|
|
|
 
|
[BrSc06]
J. Brandt and K. Schneider
Multimedia-Hardwareerweiterungen
|
|
|
|
 
|
[BrSc06a]
J. Brandt and K. Schneider
System Description Aspects as Syntactic Sugar
Forum on Specification and Design Languages (FDL)
|
|
|
|
 
|
[BrSc06b]
J. Brandt and K. Schneider
Efficient Map Overlay for Safety-Critical Embedded Systems
Industrial Embedded Systems (IES)
|
|
|
|
 
|
[Frie06]
M. Friedrich
Design and Implementation of a FCC Schedule Planner for an unmanned aircraft demonstrator
Diploma Thesis
|
|
|
|
 
|
[ScBS06]
K. Schneider and J. Brandt and T. Schüle
A Verified Compiler for Synchronous Programs with Local Declarations
Electronic Notes in Theoretical Computer Science (ENTCS)
|
|
|
|
 
|
[ScBV06a]
K. Schneider and J. Brandt and E. Vecchié
Modular Compilation of Synchronous Programs
Distributed and Parallel Embedded Systems (DIPES)
|
|
|
|
 
|
[ScBV06b]
K. Schneider and J. Brandt and E. Vecchié
Efficient Code Generation from Synchronous Programs
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[ScST06]
K. Schneider and T. Schüle and M. Trapp
Verifying the Adaptation Behavior of Embedded Systems
Software Engineering for Adaptive and Self-Managing Systems (SEAMS)
|
|
|
|
 
|
[ScSc06a]
K. Schneider and T. Schüle
A Framework for Verifying and Implementing Embedded Systems
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[Schn06a]
K. Schneider
Book Review: `A Practical Theory of Reactive Systems'
The Computer Journal
|
|
|
|
 
|
[Wagn06]
C. Wagner
Automatenbasierte Entscheidungsverfahren für Presburger-Arithmetik
Diploma Thesis
|
|
|
|
 
|
[BrSc05]
J. Brandt and K. Schneider
Using Three-Valued Logic to Specify and Verify Algorithms of Computational Geometry
International Conference on Formal Engineering Methods (ICFEM)
|
|
|
|
 
|
[BrSc05a]
J. Brandt and K. Schneider
Dependable Polygon-Processing Algorithms for Safety-Critical Embedded Systems
Embedded and Ubiquitous Computing (EUC)
|
|
|
|
 
|
[Cron05]
B. Cronauer
XML-basierte Konfiguration von Steuergeräten
Diploma Thesis
|
|
|
|
 
|
[MoSc05]
A. Morgenstern and K. Schneider
A Unified Model Checking Framework for the Supervisor Synthesis Problem
Games for Logic and Programming Languages
|
|
|
|
 
|
[MoSc05a]
A. Morgenstern and K. Schneider
Synthesizing Deterministic Controllers in Supervisory Control
Informatics in Control, Automation and Robotics (ICINCO)
|
|
|
|
 
|
[MoSc05b]
A. Morgenstern and K. Schneider
Using Model Checking to Solve Supervisor Synthesis Problems
Conference on Decision and Control and European Control Conference (CDC/ECC)
|
|
|
|
 
|
[MoSc05c]
A. Morgenstern and K. Schneider
Using Model Checking to Solve Supervisor Synthesis Problems
Presentation
|
|
|
|
 
|
[MoSc05d]
A. Morgenstern and K. Schneider
Synthesizing Deterministic Controllers in Supervisory Control
Presentation
|
|
|
|
 
|
[SBST05a]
K. Schneider and J. Brandt and T. Schüle and T. Türk
Improving Constructiveness in Code Generators
Synchronous Languages, Applications, and Programming (SLAP)
|
|
|
|
 
|
[SBST05b]
K. Schneider and J. Brandt and T. Schüle and T. Türk
Maximal Causality Analysis
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[ScSc05]
T. Schüle and K. Schneider
Three-Valued Logic in Bounded Model Checking
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[ScSc05a]
K. Schneider and T. Schüle
Averest: Specification, Verification, and Implementation of Reactive Systems
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[Schm05]
M. Schmidt
An Algorithm for Restriction of Finite Automata
Diploma Thesis
|
|
|
|
 
|
[TuSc05]
T. Türk and K. Schneider
From PSL to LTL: A Formal Validation in HOL
Theorem Proving in Higher Order Logics (TPHOL)
|
|
|
|
 
|
[TuSc05a]
T. Türk and K. Schneider
Relationship between Alternating omega-Automata and Symbolically Represented Nondeterministic omega-Automata
Technical Report
|
|
|
|
 
|
[Tuer05]
T. Türk
A Hierarchy for Accellera's Property Specification Language
Diploma Thesis
|
|
|
|
 
|
[Wagn05a]
C. Wagner
Evaluierung von Algorithmen zur Berechnung fairer Pfade
Project Thesis
|
|
|
|
 
|
[ZiSc05]
R. Ziller and K. Schneider
Combining Supervisor Synthesis and Model Checking
ACM Transactions on Embedded Computing Systems (TECS)
|
|
|
|
 
|
[BuKS04]
W. Büttner and W. Kunz and K. Schneider
Verifikation reaktiver Systeme
|
|
|
|
 
|
[Cron04]
B. Cronauer
Entwicklung eines embedded SPFH-Signal-Simulators für das John Deere GreenStar Office System
|
|
|
|
 
|
[Gent04]
R. Gentilini
Graph Algorithms for Massive Data-Sets
PhD Thesis
|
|
|
|
 
|
[Ober04]
A. Obermann
Verifikation kryptographischer Protokolle mit Baumtransduktoren
Diploma Thesis
|
|
|
|
 
|
[ScBS04a]
K. Schneider and J. Brandt and T. Schüle
A Verified Compiler for Synchronous Programs with Local Declarations (proceedings version)
Synchronous Languages, Applications, and Programming (SLAP)
|
|
|
|
 
|
[ScBS04b]
K. Schneider and J. Brandt and T. Schüle
Causality Analysis of Synchronous Programs with Delayed Actions
Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
|
|
|
|
 
|
[ScSc04]
T. Schüle and K. Schneider
Global vs. Local Model Checking of Infinite State Systems
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[ScSc04a]
T. Schüle and K. Schneider
Abstraction of Assembler Programs for Symbolic Worst Case Execution Time Analysis
Design Automation Conference (DAC)
|
|
|
|
 
|
[ScSc04b]
T. Schüle and K. Schneider
Bounded Model Checking of Infinite State Systems: Exploiting the Automata Hierarchy
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[ScSc04c]
T. Schüle and K. Schneider
Global vs. Local Model Checking: A Comparison of Verification Techniques for Infinite State Systems
Software Engineering and Formal Methods (SEFM)
|
|
|
|
 
|
[Webe04]
J. Weber
Entwurf eines RISC Prozessors mit synchronen Sprachen
Diploma Thesis
|
|
|
|
 
|
[Bran03]
J. Brandt
2D-Polygon-Clipping Algorithmen für eingebettete Echtzeitsysteme
Diploma Thesis
|
|
|
|
 
|
[LoSM03a]
G. Logothetis and K. Schneider and C. Metzler
Exact Low-Level Runtime Analysis of Synchronous Programs for Formal Verification of Real-Time Systems
Forum on Specification and Design Languages (FDL)
|
|
|
|
 
|
[LoSM03b]
G. Logothetis and K. Schneider and C. Metzler
Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification
Symposium on Integrated Circuits and System Design (SBCCI)
|
|
|
|
 
|
[LoSM03c]
G. Logothetis and K. Schneider and C. Metzler
Generating Formal Models for Real-Time Verification by Exact Low-Level Runtime Analysis of Synchronous Programs
Real-Time Systems Symposium (RTSS)
|
|
|
|
 
|
[LoSc03]
G. Logothetis and K. Schneider
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration
Design, Automation and Test in Europe (DATE)
|
|
|
|
 
|
[Metz03]
C. Metzler
WCET-Analyse mit symbolischen Verfahren
Diploma Thesis
|
|
|
|
 
|
[ScSc03]
T. Schüle and K. Schneider
Exact Runtime Analysis Using Automata-Based Symbolic Simulation
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[Schn03]
K. Schneider
Verification of Reactive Systems -- Formal Methods and Algorithms
Springer
|
|
|
|
 
|
[ZiSc03a]
R.M. Ziller and K. Schneider
A $\mu$-Calculus Approach to Supervisor Synthesis
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[ZiSc03b]
R. Ziller and K. Schneider
A Generalized Approach to Supervisor Synthesis
Formal Methods and Models for Codesign (MEMOCODE)
|
|
|
|
 
|
[ZiSc03c]
R. Ziller and K. Schneider
Reducing Complexity of Supervisor Synthesis
Control Systems Design (CSD)
|
|
|
|
 
|
[BSWZ01]
M. Baldamus and K. Schneider and M. Wenz and R. Ziller
Can American Checkers be Solved by Means of Symbolic Model Checking?
Electronic Notes in Theoretical Computer Science (ENTCS)
|
|
|
|
 
|
[BaSc01]
M. Baldamus and K. Schneider
The BDD Space Complexity of Different Forms of Concurrency
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[HHKK01]
D.W. Hoffmann and L. Holt and E. Klein and T. Kropf and K. Schneider
Special Issue on the PROSPER project
|
|
|
|
 
|
[LoSc01]
G. Logothetis and K. Schneider
A New Approach to the Specification and Verification of Real-Time Systems
Euromicro Conference on Real-Time Systems (ECRTS)
|
|
|
|
 
|
[LoSc01a]
G. Logothetis and K. Schneider
Symbolic model checking of real-time systems
Temporal Representation and Reasoning (TIME)
|
|
|
|
 
|
[Muel01]
A. Müller
Entwurf und Realisierung eines eingebetteten Systems zur Steuerung eines automatisierten Kalibrierkanals für Strömungssonden
Project Thesis
|
|
|
|
 
|
[ScWe01]
K. Schneider and M. Wenz
A new method for compiling schizophrenic synchronous programs
Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
|
|
|
|
 
|
[Schn01]
K. Schneider
Exploiting Hierarchies in Temporal Logics, Finite Automata, Arithmetics, and $\mu$-Calculus for Efficiently Verifying Reactive Systems
Habilitation Thesis
|
|
|
|
 
|
[Schn01a]
K. Schneider
Embedding Imperative Synchronous Languages in Interactive Theorem Provers
Application of Concurrency to System Design (ACSD)
|
|
|
|
 
|
[Schn01b]
K. Schneider
Improving Automata Generation for Linear Temporal Logic by Considering the Automata Hierarchy
Logic for Programming, Artificial Intelligence, and Reasoning (LPAR)
|
|
|
|
 
|
[Wenz01]
M. Wenz
Codeerzeugung für die synchrone Modellierungssprache Quartz
Diploma Thesis
|
|
|
|
 
|
[BaSc99]
M. Baldamus and K. Schneider
Extending Esterel by Asynchronous Concurrency
Fachtagung zum Entwurf Integrierter Schaltungen
|
|
|
|
 
|
[HSKL99]
M. Huhn and K. Schneider and T. Kropf and G. Logothetis
Verifying Imprecisely Working Arithmetic Circuits
Design, Automation and Test in Europe (DATE)
|
|
|
|
 
|
[SSHL99]
D. Schmid and K. Schneider and M. Huhn and G. Logothetis and V. Sabelfeld
Formale Verifikation eingebetteter Systeme
Informationstechnik und Technische Informatik (it+ti)
|
|
|
|
 
|
[ScHL99]
K. Schneider and M. Huhn and G. Logothetis
Validation of Object Oriented Concurrent Designs by Model Checking
Correct Hardware Design and Verification Methods (CHARME)
|
|
|
|
 
|
[ScHL99a]
K. Schneider and M. Huhn and G. Logothetis
Validation of Object Oriented Concurrent Designs by Model Checking
|
|
|
|
 
|
[ScHo99]
K. Schneider and D.W. Hoffmann
A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata
Theorem Proving in Higher Order Logics (TPHOL)
|
|
|
|
 
|
[ScHu99]
K. Schneider and M. Huhn
Comparing Model-Checking and Term-Rewriting in the Verification of an Embedded System
Distributed and Parallel Embedded Systems (DIPES)
|
|
|
|
 
|
[ScLo99]
K. Schneider and G. Logothetis
Abstraction of Systems with Counters for Symbolic Model Checking
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[ScSa99]
K. Schneider and V. Sabelfeld
Introducing Mutual Exclusion in Esterel
Andrei Ershov Third International Conference Perspectives of Systems Informatics
|
|
|
|
 
|
[Schn99]
K. Schneider
Yet Another Look at LTL Model Checking
Correct Hardware Design and Verification Methods (CHARME)
|
|
|
|
 
|
[StSH99]
T. Stauner and K. Schneider and M. Huhn
Translating a Visual Description Technique to a Synchronous Language: From DiCharts to PURR
Formale Beschreibungstechniken für verteilte Systeme
|
|
|
|
 
|
[Stit99]
P. Stitzelberger
übersetzung von VHDL-Strukturbeschreibungen in die synchrone Beschreibungssprache PURR
Diploma Thesis
|
|
|
|
 
|
[Zimm99]
J. Zimmermann
Implementierung eines Entwurfs-und Verifikationswerkzeuges für die synchrone Programmiersprache PURR
Master Thesis
|
|
|
|
 
|
[GrSc98]
W. Grünewald and K. Schneider
Modeling and Verifying Abstract Multithreaded Systems
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[KRSW98]
T. Kropf and J. Ruf and K. Schneider and M. Wild
A Synchronous Language for Modeling and Verifying Real Time and Embedded Systems
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[KRSW98a]
T. Kropf and J. Ruf and K. Schneider and M. Wild
The Synchronous System Description Language PURR
System Design Automation
|
|
|
|
 
|
[ReSK98]
R. Reetz and K. Schneider and T. Kropf
Formal Specification in VHDL for Formal Hardware Verification
Design, Automation and Test in Europe (DATE)
|
|
|
|
 
|
[SSFS98]
I. Schreiber and J. Schönherr and E. Fordran and K. Schneider and B. Straube
Kontrollfluss-Verifikation von Algorithmen mittels Modellprüfung
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
|
|
|
|
 
|
[Schn98]
K. Schneider
Model Checking on Product Structures
Formal Methods in Computer-Aided Design (FMCAD)
|
|
|
|
 
|
[Schr98]
J. Schröder-Babo
Anwendung spezieller Modellprüfungstechniken bei der Verifikation einer mehrfähdigen Prozessorarchitektur
Project Thesis
|
|
|
|
 
|
[Zimm98]
J. Zimmermann
Verifikation der diskreten Cosinus-Transformation mittels Modellprüfung
Project Thesis
|
|
|
|
 
|
[EiSK94]
D. Eisenbiegler and K. Schneider and R. Kumar
A Functional Approach for Formalizing Regular Hardware Structures
Theorem Proving in Higher Order Logics (TPHOL)
|
|
|
|
 
|
[PoSc94]
J. Posegga and K. Schneider
A First-Order Calculus Based on Propositional BDDs
Anwendung formaler Methoden im Systementwurf
|
|
|
|
 
|
[SSSK94]
A. Schneider and B. Straube and K. Schneider and T. Kropf
Verifikation eines digitalen Netzwerkes mit Hilfe des Beweissystems HOL
Technical Report
|
|
|
|
 
|
[ScKK94]
K. Schneider and R. Kumar and T. Kropf
Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification
Theorem Proving in Higher Order Logics (TPHOL)
|
|
|
|
 
|
[ScKK94a]
K. Schneider and T. Kropf and R. Kumar
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path
European Design Automation Conference (EDAC)
|
|
|
|
 
|
[ScKK94b]
K. Schneider and T. Kropf and R. Kumar
Accelerating Tableaux Proofs using Compact Representations
Formal Methods in System Design (FMSD)
|
|
|
|
 
|
[ScKK94c]
K. Schneider and T. Kropf and R. Kumar
Why Hardware Verification Needs more than Model Checking
Theorem Proving in Higher Order Logics (TPHOL)
|
|
|
|
 
|
[ScKK94d]
K. Schneider and R. Kumar and T. Kropf
Automating Verification by Functional Abstraction at the System Level
Theorem Proving in Higher Order Logics (TPHOL)
|
|
|
|
 
|
[ScKK94e]
K. Schneider and R. Kumar and T. Kropf
Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic
Theorem Proving in Higher Order Logics (TPHOL)
|
|
|
|
 
|
[ScKK94h]
K. Schneider and T. Kropf and R. Kumar
Hardware-Verifikation braucht mehr als Model-Checking
Anwendung formaler Methoden im Systementwurf
|