Search Result
2024
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[WeSc24c] M.C. Werner and K. Schneider From Imperative Sequential Structured Text Models to Synchronous Quartz and Sequentially Constructive Models Presentation |
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[WeSc24d] M.C. Werner and K. Schneider PLCreX -- Open-Source Project for Simplification, Transformation, Analysis, and Validation of Programmable Logic Controllers Presentation |
2022
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[BhSc22a] A. Bhagyanath and K. Schneider Buffer Allocation for Exposed Datapath Architectures Presentation |
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[RaSc22a] O. Rafique and K. Schneider Data-aware Global Scheduling of Dataflow Process Networks Presentation |
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[ScBR22a] K. Schneider and A. Bhagyanath and J. Roob Virtual Buffers for Exposed Datapath Architectures Presentation |
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[ScBR22c] K. Schneider and A. Bhagyanath and J. Roob Code Generation Criteria for Buffered Exposed Datapath Architectures from Dataflow Graphs Presentation |
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[WeSc22a] M.C. Werner and K. Schneider From IEC 61131-3 Function Block Diagrams to Sequentially Constructive Statecharts Presentation |
2021
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[Schn21b] K. Schneider Translating Structured Sequential Programs to Dataflow Graphs Presentation |
2020
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[RaSc20a] O. Rafique and K. Schneider Employing OpenCL as a Standard Hardware Abstraction in a Distributed Embedded System: A Case Study Presentation |
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[RaSc20c] O. Rafique and K. Schneider SHeD: A Framework for Automatic Software Synthesis of Heterogeneous Dataflow Process Networks Presentation |
2019
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[AnSc19a] M. Anders and K. Schneider A Formal Semantics of Exposed Datapath Architectures with Buffered Processing Units Presentation |
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[RaKS19a] O. Rafique and F. Krebs and K. Schneider Generating Efficient Parallel Code from the RVC-CAL Dataflow Language Presentation |
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[RaSc19b] O. Rafique and K. Schneider Automatic Software Synthesis of Static and Dynamic Dataflow Process Networks Presentation |
2018
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[AnBS18a] M. Anders and A. Bhagyanath and K. Schneider On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units Presentation |
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[JaSc18b] T. Jain and K. Schneider Routing Partial Permutations in General Interconnection Networks based on Radix Sorting Presentation |
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[JaSc18d] T. Jain and K. Schneider Routing Partial Permutations in Interconnection Networks based on Radix Sorting Presentation |
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[JaSc18g] T. Jain and K. Schneider Optimal Self-Routing Split Modules for Radix-based Interconnection Networks Presentation |
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[RaSc18a] O. Rafique and K. Schneider A Model-based Synthesis Framework for the Execution of Dynamic Dataflow Actors Presentation |
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[ScDa18a] K. Schneider and M. Dahlem Are Synchronous Programs Logic Programs? Presentation |
2017
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[BhSc17b] A. Bhagyanath and K. Schneider Exploring Different Execution Paradigms in Exposed Datapath Architectures with Buffered Processing Units Presentation |
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[BhSc17c] A. Bhagyanath and K. Schneider Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units Presentation |
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[JaSJ17a] T. Jain and K. Schneider and A. Jain An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip Presentation |
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[JaSW17a] T. Jain and K. Schneider and F. Walk Out-of-Order Execution of Buffered Function Units in Exposed Data Path Architectures Presentation |
2016
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[BhJS16a] A. Bhagyanath and T. Jain and K. Schneider Towards Code Generation for the Synchronous Control Asynchronous Dataflow (SCAD) Architectures Presentation |
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[BhSc16a] A. Bhagyanath and K. Schneider Optimal Compilation for Exposed Datapath Architectures with Buffered Processing Units by SAT Solvers Presentation |
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[JaSB16a] T. Jain and K. Schneider and A. Bhagyanath The Selector-Tree Network: A New Self-Routing and Nonblocking Interconnection Network Presentation |
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[JaSc16a] T. Jain and K. Schneider Verifying the Concentration Property of Permutation Networks by BDDs Presentation |
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[LiSc16b] X. Li and K. Schneider Control-flow Guided Clause Generation for Property Directed Reachability Presentation |
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[LiSc16d] X. Li and K. Schneider Control-flow Guided Property Directed Reachability for Synchronous Programs Presentation |
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[RBLS16a] T. Ropertz and K. Berns and X. Li and K. Schneider Verification of Behavior-Based Control Systems in their Physical Environment Presentation |
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[RaSc16b] O. Rafique and K. Schneider Introducing MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded Systems Presentation |
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[RaSc16c] O. Rafique and K. Schneider MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded Systems Presentation |
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[SeSc16a] M. Senftleben and K. Schneider Specifying Weak Memory Consistency with Temporal Logic Presentation |
2015
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[BhJS15a] A. Bhagyanath and T. Jain and K. Schneider A Time-Predictable Model of Computation Presentation |
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[LiSc15e] X. Li and K. Schneider A Counterexample-Guided Approach to Symbolic Simulation of Hybrid Systems Presentation |
2014
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[BSBK14a] Y. Bai and K. Schneider and N. Bhardwaj and B. Katti and T. Shazadi From Clock-Driven to Data-Driven Models Presentation |
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[BSBK14b] Y. Bai and K. Schneider and N. Bhardwaj and B. Katti and T. Shazadi From Clock-Driven to Data-Driven Models Presentation |
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[BhSS14a] N. Bhardwaj and M. Senftleben and K. Schneider Abacus – A Processor Family for Education Presentation |
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[BhSc14a] A. Bhagyanath and K. Schneider TTA as Predictable Architecture for Real-Time Applications Presentation |
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[FMSS14a] F. Furbach and R. Meyer and K. Schneider and M. Senftleben Memory Model-aware Testing -- A Unified Complexity Analysis Presentation |
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[GeBS14a] M. Gesell and F. Bichued and K. Schneider Using Different Representations of Synchronous Systems in SAL Presentation |
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[KhBS14b] M.A. Ben Khadra and Y. Bai and K. Schneider Synthesis of Distributed Synchronous Specifications to SysteMoC Presentation |
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[LiSc14b] X. Li and K. Schneider Interactive Verification of Hybrid Systems Presentation |
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[RSFB14] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira and Y. Bai Using the Base Semantics given by fUML for Verification Presentation |
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[RoSF14b] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira Integrating UML Composite Structures and fUML Presentation |
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[ScWi14a] K. Schneider and A. Willenbücher A New Algorithm for Carry-Free Addition of Binary Signed-Digit Numbers Presentation |
2013
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[GeLS13] M. Gesell and X. Li and K. Schneider Interactive Verification of Cyber-physical Systems Presentation |
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[GeMS13a] M. Gesell and A. Morgenstern and K. Schneider Lifting Verification Results for Preemption Statements Presentation |
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[GeSc13b] M. Gesell and K. Schneider Modular Verification of Synchronous Programs Presentation |
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[GeSc13d] M. Gesell and K. Schneider Translating Synchronous Guarded Actions to Interleaved Guarded Actions Presentation |
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[LiBS13a] X. Li and K. Bauer and K. Schneider Interactive Verification of Cyber-physical Systems Interfacing Averest and KeYmaera Presentation |
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[MSLG13] A. Morgenstern and K. Schneider and S. Lamberti and M. Gesell From LTL to Symbolically Represented Deterministic Automata Presentation |
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[MoGS13a] A. Morgenstern and M. Gesell and K. Schneider Solving Games Using Incremental Induction Presentation |
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[RaGS13b] O. Rafique and M. Gesell and K. Schneider Generating Hardware-Specific Code at Different Abstraction Levels using Averest Presentation |
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[RoSF13b] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira Synchronous Specialization of Alf for Cyber-Physical Systems Presentation |
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[RoSF13c] A. Gerlinger Romero and K. Schneider and M. Gonçalves Vieira Ferreira Towards the Applicability of Alf to Model Cyber-Physical Systems Presentation |
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[WiSc13a] A. Willenbücher and K. Schneider Automatic Hard Block Inference on FPGAs Presentation |
2012
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[BaBS12d] D. Baudisch and J. Brandt and K. Schneider Out-Of-Order Execution of Synchronous Data-Flow Networks Presentation |
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[BaBS12e] D. Baudisch and J. Brandt and K. Schneider Efficient Handling of Arrays in Dataflow Process Networks Presentation |
2011
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[BaBS11c] D. Baudisch and J. Brandt and K. Schneider Translating Synchronous Systems to Data-Flow Process Networks Presentation |
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[MoSc11e] A. Morgenstern and K. Schneider Synthesis of Sorting Networks using SAT Solvers Presentation |
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[MoSc11f] A. Morgenstern and K. Schneider Program Sketching via CTL* Model Checking Presentation |
2010
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[BaBS10c] D. Baudisch and J. Brandt and K. Schneider Multithreaded Code from Synchronous Programs: Extracting Independent Threads for OpenMP Presentation |
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[BaBS10d] D. Baudisch and J. Brandt and K. Schneider Multithreaded Code from Synchronous Programs: Generating Software Pipelines for OpenMP Presentation |
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[BaBS10e] D. Baudisch and J. Brandt and K. Schneider Dependency-Driven Distribution of Synchronous Programs Presentation |
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[MoSc10a] A. Morgenstern and K. Schneider Exploiting the Temporal Logic Hierarchy and the Non-Confluence Property for Efficient LTL Synthesis Presentation |
2009
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[BaGS09c] D. Baudisch and M. Gesell and K. Schneider Online Exercise System -- A Web-Based Tool for Administration and Automatic Correction of Exercises Presentation |
2008
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[MoSL08b] A. Morgenstern and K. Schneider and S. Lamberti Generating Deterministic $\omega$-Automata for most LTL formulas by the Breakpoint Construction Presentation |
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[MoSc08c] A. Morgenstern and K. Schneider From LTL to Symbolically Represented Deterministic Automata Presentation |
2005
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[MoSc05c] A. Morgenstern and K. Schneider Using Model Checking to Solve Supervisor Synthesis Problems Presentation |
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[MoSc05d] A. Morgenstern and K. Schneider Synthesizing Deterministic Controllers in Supervisory Control Presentation |