Search Result
2024
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[Bitt24] C. Bittes An Evaluation of Cold Boot Attacks |
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[Bitt24a] C. Bittes An Evaluation of Cold Boot Attacks |
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[Chee24] A.U. Cheema Fault Attacks |
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[Chee24a] A.U. Cheema Fault Attacks |
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[Chri24] K. Christmann Power Side-Channel Attacks |
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[Chri24a] K. Christmann Power Side-Channel Attacks |
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[Fass24] A. Faßbender Empirische Evaluierung der Effekte von Hardwarebeschleunigung auf quantenresistente Kryptographie im TLS 1.3 Protokoll Bachelor Thesis |
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[Geup24] H. Geupel Mitigating Branch Prediction Attacks - A Comparison |
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[Geup24a] H. Geupel Mitigating Branch Prediction Attacks - A Comparison |
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[Hemm24] L. Hemmerling Hardware-based Control-Flow Integrity: An Overview |
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[Hemm24a] L. Hemmerling Hardware-based Control-Flow Integrity: An Overview |
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[Jose24] A.P. Jose A Microkernel based solution for SAFE Deadline Monitoring Master Thesis |
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[Kapl24] T. Kaplan Firmware Vulnerabilities |
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[Kapl24a] T. Kaplan Firmware Vulnerabilities |
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[Luet24] A. Lütke-Bordewick Physical Unclonable Functions: Use Cases, Implementations and Exploits |
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[Luet24a] A. Lütke-Bordewick Physical Unclonable Functions: Use Cases, Implementations and Exploits |
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[Ried24] S. Riedel A Survey about Acoustic and Electromagnetic Attacks and other Physical Side Channels |
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[Ried24a] S. Riedel A Survey about Acoustic and Electromagnetic Attacks and other Physical Side Channels |
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[Saji24] K.B. Sajikumar Modeling Hazardous Events in Automated Driving for Probabilistic Approach of Test Instrumentation Master Thesis |
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[Stra24a] T.-F. Straub Hardware trojans |
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[Stra24b] T.-F. Straub Hardware trojans |
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[Tego24] F. Tego Efficient Translation of Linear Temporal Logic to Deterministic Automata Master Thesis |
2023
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[BKMJ23] E. Borth and S. Klaaßen and F. Mbikhoum and A.P. Jose Report on OpenMP Project |
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[Bort23] E. Borth Generating parallel OpenCL and OpenMP Programs from Dataflow Graphs Bachelor Thesis |
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[Bort23a] E. Borth Generating parallel OpenCL and OpenMP Programs from Dataflow Graphs Presentation |
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[Diet23] F. Dietrich Is the future all optical? |
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[Diet23a] F. Dietrich Tail Duplication for Compilation for Buffered Exposed Datapath Architectures Bachelor Thesis |
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[Ejla23] N. Ejlali Representing threat models by the Open Security Controls Assessment Language (OSCAL) Master Thesis |
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[Frei23] J. Freiermuth Echtzeit-Schaltassistent fü̈r Elektrofahrzeuge mit Schaltgetriebe Master Thesis |
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[Frie23] E. Friedek A Study of Coarse-Grained Reconfigurable Architectures |
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[Gupt23] A. Gupta A Model Driven Migration of Complex Legacy Solutions to a new ABAP software stack Master Thesis |
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[Haeu23] M. Häuser Designing a Secure and Space-Efficient Executable File Format for the Unified Extensible Firmware Interface Master Thesis |
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[Kerc23] N. Kercher Code Generation for Buffered Exposed Datapath Architectures Master Thesis |
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[Kozi23] S. Koziakov Towards a safe user-level virtual machine monitor for L4Re Master Thesis |
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[Kuag23] M. Kuaguim Synchronous Language Approaches: An Overview |
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[Misr23] S. Misra Power-Efficient Computing Strategies: Exploring DVFS, DPM, and Aggressive Scheduling for Enhanced Performance and Energy Savings |
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[Neuh23] Y. Neuhard Developing an Augmented Reality Solution with GPU/CUDA Support to Evaluate and Visualize V2X Scenarios in a Driving Vehicle Master Thesis |
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[Pola23] P.J. Polavarapu A Survey of Tiny Processors |
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[Schr23] E. Schreiner Using Dataflow Models for Real-Time Systems |
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[Sonn23] L. Sonnenfeld FPGA Graphics: A Proposition for a Graphics Pipeline Architecture for FPGAs |
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[Wern23] L. Werner Performance Evaluation of Interconnection Networks on Processors Bachelor Thesis |
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[Zeun23] J. Zeunert Assessing the Security of Integrating SystemVerilog Synthesis and Simulation in Untrusted Environments Master Thesis |
2022
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[Balk22] D. Balke Consistency and Robustness in an Event-sourced System Bachelor Thesis |
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[Burg22] T. Burgers A Study on the Model-based Development of Automotive Software |
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[Chri22] F. Christoph Lambda Calculus and How It Shapes Programming Languages Today |
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[Goeb22] P. Göbel Methoden zur Prozessorverifikation und zum Testen |
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[Haeu22] M. Häuser Use of Symbolic Execution for Verification |
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[Luet22] A.D. Lütke-Bordewick Instruction Scheduling for Exposed Datapath Architectures Bachelor Thesis |
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[Mahm22] H.M.A. Mahmoud Mapping Dataflow Process Networks on Real-time Operating Systems Bachelor Thesis |
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[Nand22] M. Nandanwar Formal Verification with Petri Nets |
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[Nara22] S.S. Naragund Sequencing Constraints in Contract-based verification Master Thesis |
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[Nara22a] A. Narasimhan Evaluation of Binary Moment Diagrams Master Thesis |
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[Neuh22] Y. Neuhard A Comparison of Real-time Operating Systems for Embedded Computing |
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[Rame22] R. Ramesh Decompilation of Move Programs to Dataflow Process Networks Master Thesis |
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[Scha22] O. Schauer SATA and Beyond: Overview of Storage Hardware Interfaces |
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[Schi22] E. Schiebelbein The Multi-Paradigm Synchronous Programming Language LEA |
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[Thei22] D. Theis Symbolic Execution of Synchronous Quartz Programs Master Thesis |
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[Upad22] S. Upadhye Data-Driven System Design Based on the Development Data Master Thesis |
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[Wern22] L. Werner s |
2021
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[Dahl21] M. Dahlem Using Enhanced Logic Programming Semantics for Extending and Optimizing Synchronous System Design PhD Thesis |
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[Feth21] M.T. Feth A Resource-Constrained Implementation of an Educational Microprocessor Bachelor Thesis |
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[Goka21] G. Gokaj Analysis of a Tableau-based Decision Procedure for CTL* Bachelor Thesis |
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[Hack21] A. Hackenberg Survey of Open Source Processor Implementations |
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[Herz21] M. Herzog FPGAs in teaching: Applications and Methods |
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[Kock21] F. Kockelke An Overview of Functional Reactive Programming |
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[Nava21] R.F. Navarro The Role of Computer Science in Combating COVID-19 |
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[Rafi21] O. Rafique Embedded Software Synthesis using Heterogeneous Dataflow Models PhD Thesis |
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[Sale21] A. Saleem Steuerwerkssynthese für Datenflussprogramme Bachelor Thesis |
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[Schn21c] A. Schneiders A Comparison of Exposed Datapath and Conventional Processor Architectures Master Thesis |
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[Schr21] E. Schreiner CNN Beschleuniger |
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[Stei21] M. Stein Optimizing Overhead in Compilation for SCAD Architectures Master Thesis |
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[Stoc21] J. Stock Konfigurationsmanagement mit fachlichen Nutzern als Zielgruppe für ein technisch komplexes System Bachelor Thesis |
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[Stol21] A. Stoll A Survey of Forecasting Techniques for COVID-19 |
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[Suik21] M. Suiker The SACRES Project: Distributed and Modular Code Generation |
2020
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[Bhag20] A. Bhagyanath Code Generation for Synchronous Control Asynchronous Dataflow Architectures PhD Thesis |
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[Drew20] M. Drewniok Programmtransformation zur Vereinfachung des Kontrollflusses Bachelor Thesis |
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[Drew20a] M. Drewniok Programmtransformation zur Vereinfachung des Kontrollflusses Presentation |
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[Haid20] S.M. Haider Evaluating Scheduling Strategies for Executing Neural Networks on OpenCL Platforms Master Thesis |
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[Haid20a] S.M. Haider Evaluating Scheduling Strategies for Executing Neural Networks on OpenCL Platforms Presentation |
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[Heil20] P. Heiler Seminar: Live-Verification while Programming: Dafny |
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[Heil20a] P. Heiler Seminar: Live-Verification while Programming: Dafny Presentation |
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[Hell20] S. Heller Seminar: On Security Features in Commercial Processors |
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[Hell20a] S. Heller Seminar: On Security Features in Commercial Processors Presentation |
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[Lill20] M. Lill Comparing SSA Code Transformations in Compilers Bachelor Thesis |
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[Luet20] A. Lütke-Bordewick Seminar: A Study on the Development of IoT Systems |
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[Luet20a] A. Lütke-Bordewick Seminar: A Study on the Development of IoT Systems Presentation |
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[Pfaf20] A. Pfaff Seminar: A study of AEGIS and MI6 Secure Processor Architectures |
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[Pfaf20a] A. Pfaff Seminar: A study of AEGIS and MI6 Secure Processor Architectures Presentation |
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[Rama20] P.K. Ramachandran Verification of SysML Models using Hybrid-Testbeds with Model-in-the-Loop Simulations Master Thesis |
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[Subr20] S.N. Subramanya An Evaluation of WebAssembly on Edge Devices for IoT Master Thesis |
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[Tiss20] S. Tissen Entwicklung eines Machine-Learning Modells zur Auswertung von Überlebensdaten und Bereitstellung als Web-Service Bachelor Thesis |
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[Zeun20] J. Zeunert Seminar: Spectre and Meltdown -- A tamed ghost? |
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[Zeun20a] J. Zeunert Seminar: Spectre and Meltdown -- A tamed ghost? Presentation |
2019
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[AnKL19] M. Anders and S. Kwasigroch and M. Lederer Applied Verification Tasks Project Thesis |
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[Desh19] P.D. Deshmukh Verification of AUTOSAR Basis Software Master Thesis |
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[Ego19] L. Ego Memory Synchronization Techniques |
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[Ego19a] L. Ego Memory Synchronization Techniques Presentation |
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[FBAG19] J. Frömmer and N. Bannow and A. Aue and C. Grimm and K. Schneider Model-Based Configuration of a Coarse-Grained Reconfigurable Architecture Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
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[GrSZ19] Ch. Grimm and K. Schneider and C. Zivkovich Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
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[Haid19] S.M. Haider Synthesis Framework for Executing Neural Networks on Heterogeneous Platforms Master Thesis |
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[Harc19] A. Harchandani How to Refine Support Experience Using Machine Learning Master Thesis |
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[Hass19] F. Hasselwander Lemma Generation for Induction-based Proof Rules Master Thesis |
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[Jain19] T. Jain Nonblocking On-Chip Interconnection Networks PhD Thesis |
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[KoSc19] M. Köhler and K. Schneider Inductive Proof Rules Beyond Safety Properties Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
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[Kreb19] F. Krebs A Translation Framework from RVC-CAL Dataflow Programs to OpenCL/SYCL based Implementations Master Thesis |
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[Kwas19] S. Kwasigroch Seminar: The Current State of Property Directed Reachability |
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[Kwas19a] S. Kwasigroch Seminar: The Current State of Property Directed Reachability Presentation |
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[Lede19] M. Lederer Causal Correctness as a Safety Property Bachelor Thesis |
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[Maia19] E.M. Lemos Maia (RO)BDD: History and Importance |
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[Maia19a] E.M. Lemos Maia (RO)BDD: History and Importance Presentation |
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[Moha19] M. Mohamed SIMULINK to DLL (for TSIM Plugin) Project Thesis |
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[Mukh19] P.S. Mukherjee Data-driven Control with Machine Learning for Optimization of a Cement Mill Master Thesis |
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[Neuh19] Y. Neuhard A Comparative Study on Existing Dataflow-oriented Frameworks |
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[Neuh19a] Y. Neuhard A Comparative Study on Existing Dataflow-oriented Frameworks Presentation |
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[Pete19] A.K. Peters Intuitionistic Logic: A View of its Evolution |
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[Pete19a] A.K. Peters Intuitionistic Logic: A View of its Evolution Presentation |
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[Schn19] A. Schneiders Software and Formal Verification in Avionics |
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[Schn19a] A. Schneiders Software and Formal Verification in Avionics Presentation |
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[Scho19] A. Schönitz Speculative Execution in Data Flow Processors |
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[Scho19a] A. Schönitz Speculative Execution in Data Flow Processors Presentation |
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[Senf19] M. Senftleben Modelling Memory Consistency Models for Formal Verification PhD Thesis |
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[Thei19] D. Theis Restrukturierung der API und Serverkomponente eines mobilen Spiels zur Optimierung der Sicherheit Bachelor Thesis |
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[Tiss19] S. Tissen Weak Memory Semantics |
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[Tiss19a] S. Tissen Weak Memory Semantics Presentation |
2018
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[Ande18] M. Anders Foundations for Verifiable Reactive Systems on Exposed Datapath Architectures with Buffered Processing Units Project Thesis |
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[Ande18a] M. Anders Foundations for Verifiable Reactive Systems on Exposed Datapath Architectures with Buffered Processing Units Presentation |
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[Beja18] S. Bejai Compilation Techniques for Increasing Instruction-level Parallelism for the SCAD Machine |
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[Beja18a] S. Bejai Compilation Techniques for Increasing Instruction-level Parallelism for the SCAD Machine Presentation |
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[Betz18] A. Betz A survey on OpenCL-based design flows for executing DPNs |
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[Betz18a] A. Betz A survey on OpenCL-based design flows for executing DPNs Presentation |
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[Bhat18] S.N. Bhat Robustness Assessment of Linux by Simulation-Based Physical Fault Injection in System Calls Master Thesis |
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[Bone18] Y. Bonenberger Ordering events in distributed systems: A review |
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[Bone18a] Y. Bonenberger Ordering events in distributed systems: A review Presentation |
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[Bonk18] J. Bonkile Development Tools Tailored for Serverless Cloud Computing Master Thesis |
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[Buss18] L. Busser Evaluating Learning Algorithms for Regular Expressions Bachelor Thesis |
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[Das18a] T. Das Classification of Warranty Claim Data using Supervised Machine Learning Algorithm SVM (Support Vector Machine) Master Thesis |
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[Dsou18] E.A. Dsouza Optical Communication in High Voltage Battery Systems Master Thesis |
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[Dsou18a] E.A. Dsouza Optical Communication in High Voltage Battery Systems Presentation |
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[Geor18] G. Georgopoulos Operational Semantics of Memory System Implementations Master Thesis |
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[Hubr18] J. Hubrich Cracking Enigma, a (short) Summary of the past |
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[Hubr18a] J. Hubrich Cracking Enigma, a (short) Summary of the past Presentation |
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[Meck18] D. Meckel Fundamentals of Robotics Verification |
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[Meck18a] D. Meckel Fundamentals of Robotics Verification Presentation |
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[Mohe18] S. Mohebbi The history of P vs. NP |
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[Mohe18a] S. Mohebbi The history of P vs. NP Presentation |
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[Muel18] P. Müller Control flow and data flow in processors |
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[Muel18a] P. Müller Control flow and data flow in processors Presentation |
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[Muen18] K. Münch Lazy Grounding und seine Mö̈glichkeiten |
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[Muen18a] K. Münch Lazy Grounding und seine Mö̈glichkeiten Presentation |
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[Rohr18] N. Rohr GOTO Statement: A Balanced View |
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[Rohr18a] N. Rohr GOTO Statement: A Balanced View Presentation |
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[Schn18] A. Schneiders Using Static-Single-Information-Form for SCAD Code Generation Bachelor Thesis |
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[Schu18] S. Schumb Evaluating Interconnection Networks for Exposed Datapath Architectures Master Thesis |
2017
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[Ande17] M. Anders Complexity Analysis of Code Generation for the SCAD Machine Bachelor Thesis |
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[Basa17] S.R. Basavaraju Application-specific Configuration of Exposed Datapath Architectures Master Thesis |
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[BhSc17] A. Bhagyanath and K. Schneider Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units Application of Concurrency to System Design (ACSD) |
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[Grue17] E. Grüner Systematic Testing and Stateless Model Checking |
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[Haif17] F. Haifani Antichain Optimization using Simulation Relations for Context-Free Games Master Thesis |
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[Jede17] E. Jedermann Application-specific Computing Features in Processors |
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[Kann17] S. Kannoth Synchronous Modelling and Formal Verification of Train Command Management Systems Master Thesis |
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[Koen17] M. Koenig Complexity Analysis of Register Allocation |
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[Koen17a] M. Koenig Komplexitätsanalyse der Speicherallokation Presentation |
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[Kreb17] F. Krebs Timing Predictability of Processors |
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[Kreb17a] F. Krebs Timing Predictability of Processors Presentation |
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[Kwas17] S. Kwasigroch Execution Paradigms in Dataflow Processors |
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[LeSc17] A. Legay and K. Schneider Message from the ACSD 2017 Program Chairs Application of Concurrency to System Design (ACSD) |
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[Leon17] V. Leonhardt Hoare Calculus for SIMT Programms |
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[Leon17a] V. Leonhardt Hoare Calculus for SIMT Programs Presentation |
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[Li17] X. Li Induction-based Verification of Synchronous and Hybrid Programs PhD Thesis |
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[Neum17] E. Neumann Algorithms for Context-free Games: A Comparison of Saturation, Guess and Check, and Summarization Master Thesis |
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[Roob17] J. Roob OpenCL Implementation of Exposed Data Path Architectures as General Purpose Accelerators Master Thesis |
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[Schm17a] F. Schmidt Time Predictable Computer Architecture Presentation |
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[Schm17b] F. Schmidt Time Predictable Computer Architectures |
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[Stat17] M. Stather Entwicklung einer Kommunikationskomponente mit Sensor-/Aktorinterface auf einem FPGA für das Finroc-Projekt Bachelor Thesis |
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[Stut17] F.M. Stutz Operations on a Symbolic Domain for Synthesis Bachelor Thesis |
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[TaDS17] J.-P. Talpin and P. Derler and K. Schneider Message from the Chairs Formal Methods and Models for Codesign (MEMOCODE) |
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[Wend17] J. Wendel A selective study on model-based design frameworks |
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[Wend17a] J. Wendel A Selective Study on Model-based Design Frameworks Presentation |
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[Wolf17] K. Wolff Code Generation for Dataflow Processors |
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[Zaid17] S. Zaidi Performance of OpenCL in Multicore Processors |
2016
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[Bai16] Y. Bai Model-based Design of Embedded Systems by Desynchronization PhD Thesis |
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[BhSc16] A. Bhagyanath and K. Schneider Optimal Compilation for Exposed Datapath Architectures with Buffered Processing Units by SAT Solvers Formal Methods and Models for Codesign (MEMOCODE) |
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[Buss16] L. Busser Inference of regular expressions/grammars for given data entities |
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[Dein16] D. Deiniger Application of Factored Representations from Probabilistic Graphical Models to Probabilistic Verification Master Thesis |
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[Desh16] P.D. Deshmukh Evaluation and comparison of inter-processor communication techniques in model-based design flows/tools |
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[Geor16] G. Georgopoulos Memory Consistency Models of Modern CPUs |
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[Geor16a] G. Georgopoulos Memory Consistency Models of Modern CPUs Presentation |
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[Harm16] C. Harms Evaluation of FPGA-based Implementations of Interconnection Networks Master Thesis |
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[Heer16] M. Heer Verification Condition Generation for Hybrid Systems described by Synchronous Languages Master Thesis |
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[Herr16] F. Herrmann State of the Art in Temporal Logic Verification |
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[Herr16a] F. Herrmann State of the Art in Temporal Logic Verification Presentation |
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[Huse16] J. Husemann A Study of Queue Machines |
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[JaSc16] T. Jain and K. Schneider Verifying the Concentration Property of Permutation Networks by BDDs Formal Methods and Models for Codesign (MEMOCODE) |
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[John16] M.R. John Static Instruction Scheduling for Transport Triggered Architectures Master Thesis |
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[Kabo16] A. Kabouteh Formal Method Based Analysis of an Ophthalmic Surgical Robot Considering Hard Real-Time Constraints Master Thesis |
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[Kann16] S. Kannoth A Survey of Real-Time Interconnects |
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[Krem16] M. Kremer Worst Case Reaction Time (WCRT) Analysis Techniques for Synchronous Programs |
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[LiSc16c] X. Li and K. Schneider Control-flow Guided Property Directed Reachability for Synchronous Programs Formal Methods and Models for Codesign (MEMOCODE) |
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[Pand16] G. Pandit Compilation Techniques for Reactive Systems |
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[Rao16] A. Rao Implementation of a Software Emulator to recreate I2C Sensor Communication Master Thesis |
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[Schu16] S. Schumb A Survey of Reactive Processor Architectures |
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[Schu16a] S. Schumb A Survey of Reactive Processor Architectures Presentation |
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[TaLS16] J.P. Talpin and E. Leonard and K. Schneider Welcome Message from the Chairs Formal Methods and Models for Codesign (MEMOCODE) |
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[Walk16a] F. Walk Out-of-Order Execution Within Functional Units of the SCAD Architecture Master Thesis |
2015
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[Ashr15] K. Ashraf HW/SW Co-design and Implementation of a Fountain Code for an FPGA System-on-Chip Master Thesis |
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[Basa15] S.R. Basavaraju WCET-centric Scratchpad Memory Allocation |
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[Basa15a] S.R. Basavaraju WCET-centric Scratchpad Memory Allocation Presentation |
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[Betz15] A. Betz x86 Memory Consistency |
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[Bich15] F. Bichued Verification of Microprocessors Master Thesis |
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[Blat15] D. Blatner Automatisierte Transformationen von Petri-Netzen zur detaillierten Ablaufkontrolle in verteilten Laufzeitsystemen Master Thesis |
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[Eswa15] A. Eswarappa AUTOSAR |
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[Faus15] M. Faust Dataflow processor architecture implementation survey |
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[Faus15a] M. Faust Dataflow processor architecture implementation survey Presentation |
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[Froe15] J. Frömmer Hoare Calculi for Parallel Programs |
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[Garc15] H. Lázaro García Using UVM for Mixed-Signal Verification with IGBT Driver Context Master Thesis |
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[Grei15] T. Greiner The use of weak consistency models in cloud storage |
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[Harm15] C. Harms Branch Prediction in WCET Analysis |
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[Harm15a] C. Harms Branch Prediction in WCET Analysis Presentation |
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[Jede15] E. Jedermann Exposed Datapath Processor Architecture Implementation Survey |
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[Jede15a] E. Jedermann Exposed Datapath Processor Architecture Implementation Survey Presentation |
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[Klip15] N. Klipphahn Concurrent Model Checking -- Systematic testing/Stateless Model Checking |
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[Klip15a] N. Klipphahn Concurrent Model Checking -- Systematic testing/Stateless Model Checking Presentation |
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[Kolh15] A. Kolhapurkar Functional Safety: ISO26262 |
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[Lang15] D. Langguth Scratchpad memory vs Caches -- Performance and Predictability Comparison |
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[Lang15a] D. Langguth Scratchpad memory vs Caches -- Performance and Predictability Comparison Presentation |
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[Nogu15] C. Pereira Nogueira Caches in Worst Case Execution Time (WCET) Analysis |
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[Nogu15a] C. Pereira Nogueira Caches in Worst Case Execution Time (WCET) Analysis Presentation |
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[Pahl15] P. Pahlevannejad Speculative Relaxation of Memory Consistency |
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[Pahl15a] P. Pahlevannejad Speculative Relaxation of Memory Consistency Presentation |
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[Schu15] S. Schumb Hardware Generation for Transport Triggered Architectures Bachelor Thesis |
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[Shaz15] T. Shazadi Evaluation of Dataflow Process Networks Mapping on Multi-core Processors Master Thesis |
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[Stra15] J. Stratmann Implementation and Verification of IEEE-conform Floating-Point Arithmetic Master Thesis |
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[Tria15] A. Triambak Dynamic Scheduling of Instructions in Transport Triggered Architecture based Processors Master Thesis |
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[Zhan15] H. Zhang E-Gas Überwachungskonzept |
2014
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[Adam14] J. Adamczyk Automotive Application: Engine Control |
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[Bill14] J. Billert Automotive Operating Systems: OSEK/VDX |
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[Dahl14] M. Dahlem Interactive Verification of Synchronous Systems in HOL Master Thesis |
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[Espe14] D. Espen Adaptive Cruise Control |
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[Gese14] M. Gesell Interactive Verification of Synchronous Systems PhD Thesis |
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[Heer14] M. Heer Assembler Code-Generierung aus synchronen Aktionen Bachelor Thesis |
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[Heil14] P. Heiler CAN -- Controller Area Network |
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[Hubr14] J. Hubrich Fahrdynamikregelung |
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[Kaes14] M. Kaesberger Fahrzeugdiagnose |
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[Kimp14] M. Kimpel Automotive Software Modules and Interfaces: ASAM MDX |
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[Knob14] J.B. Knobloch LIN-Bus |
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[Maca14] M.N. Basurto Macavilca Endochrony of Distributed Systems Diploma Thesis |
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[Rede14] M. Reder Code Generation for Transport Triggered Architecture Bachelor Thesis |
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[Rome14] A. Gerlinger Romero Hybrid fUML: A Hybrid Synchronous Language PhD Thesis |
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[Roob14] J. Roob A Hardware Abstraction Layer for Model-based Design of Embedded Systems Bachelor Thesis |
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[SCSO14] K. Schneider and N. Chang and Y. Shin and S. Ozev International Conference on Computer Design (ICCD) |
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[Schm14b] F. Schmidt Automotive Communication Architectures: MOST |
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[Schn14] F. Schnicke ASCET-MD |
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[Thie14] D. Thielsch Analysis of Concurrency in Synchronous Systems Master Thesis |
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[Tria14] A. Triambak Timing Anomalies and WCET Analysis |
2013
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[BSCO13] G. Byrd and K. Schneider and N. Chang and S. Ozev International Conference on Computer Design (ICCD) |
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[Baud13] D. Baudisch Synthesis of Synchronous Programs to Parallel Software Architectures PhD Thesis |
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[Bich13] F. Bichued Cyber Physical System Verification with SAL |
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[Bich13a] F. Bichued Cyber Physical System Verification with SAL Presentation |
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[Bran13] J. Brandt Synchronous Models for Embedded Software Habilitation Thesis |
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[Ciol13] G.A. Ciolacu Introducing Simulation of Hybrid Systems with the Modelica Tool |
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[Ciol13a] G.A. Ciolacu Introducing Simulation of Hybrid Systems with the Modelica Tool Presentation |
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[Gemu13a] M. Gemünde Clock Refinement in Imperative Synchronous Programs PhD Thesis |
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[Humb13] Y. Humbert Umsetzung und Vergleich der Ausführung einer rechenintensiven Echtzeitanwendung mittels OpenMP und CUDA am Beispiel des Beamforming-Algorithmus Master Thesis |
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[Khad13] M.A. Ben Khadra A Model-based Approach To Sychronous Elastic Systems Master Thesis |
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[Rafi13] O. Rafique Design, Development, and Integration of a Wireless Communication Unit in ConceptCar Master Thesis |
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[Schu13c] S. Schumb Cyber Physical System Verification Seminar: Event-B |
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[Schu13d] S. Schumb Cyber Physical System Verification Seminar: Event-B Presentation |
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[Senf13] M. Senftleben Operational Characterization of Weak Memory Consistency Models Master Thesis |
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[Walk13] F. Walk Parallel Software Generated from Synchronous Programs -- A Performance Evaluation Using a Ray Tracer Bachelor Thesis |
2012
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[BaSc12b] D. Baudisch and K. Schneider GPGPU Architectures -- Compiler Techniques and Applications |
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[Baue12] K. Bauer A New Modelling Language for Cyber-physical Systems PhD Thesis |
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[Blat12] D. Blatner OpenACC and the PGI Compiler |
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[Blat12a] D. Blatner OpenACC and the PGI Compiler Presentation |
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[BrSc12] J. Brandt and K. Schneider Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) |
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[Eick12] T. Eickhoff Program Sketching Using Craig Interpolants Bachelor Thesis |
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[Grae12a] M. Gräfe GPU Architektur und Programmiermö̈glichkeiten fü̈r GPGPU-Anwendungen Presentation |
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[Grae12b] M. Gräfe GPU Architektur und Programmiermö̈glichkeiten fü̈r GPGPU-Anwendungen |
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[Humb12] Y. Humbert Simulation digitaler Schaltungen auf GPUs |
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[Humb12a] Y. Humbert Simulation digitaler Schaltungen auf GPUs Presentation |
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[Koel12] J. Kölsch Automatische C-to-CUDA Code Generierung |
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[Koel12a] J. Kölsch Automatische C-to-CUDA Code Generierung Presentation |
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[Liet12] B. Lietzow A Domain Specific Language for the Synthesis of Networked Embedded Systems Master Thesis |
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[Ratz12] A. Ratzke An introduction to the research on Scratchpad memory with focus on performance improvement -- Instruction SPM, SPM on Multicoresystems and SPM on Multitaskingsystems |
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[Ratz12a] A. Ratzke An introduction to the research on Scratchpad memory with focus on performance improvement -- Instruction SPM, SPM on Multicoresystems and SPM on Multitaskingsystems Presentation |
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[Roob12] J. Roob An Introduction to the Research on Scratchpad Memory: Definition, Hardware, Known Implementations and WCET Optimisation |
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[Roob12a] J. Roob An Introduction to the Research on Scratchpad Memory: Definition, Hardware, Known Implementations and WCET Optimisation Presentation |
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[Senf12] M. Senftleben Dataflow Programming on GPUs |
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[Senf12a] M. Senftleben Dataflow Programming on GPUs Presentation |
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[Stra12] J. Stratmann Design and Implementation of a Floating-Point Application Specific Instruction Set Processor Bachelor Thesis |
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[TBBS12] S. Tahar and G. Byrd and P. Bose and K. Schneider International Conference on Computer Design (ICCD) |
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[Thie12] D. Thielsch Criteria of Endo/Isochrony in Quartz Bachelor Thesis |
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[Thie12a] D. Thielsch Verifikation auf paralleler Hardware Presentation |
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[Thie12b] D. Thielsch Verifikation auf paralleler Hardware |
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[Thul12] J. Thull Ein Testkonzept für Efficient XML Interchange (EXI) im Automobilbereich Master Thesis |
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[Walk12] F. Walk Porting CUDA code to multicore CPUs and other platforms |
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[Walk12a] F. Walk Porting CUDA code to multicore CPUs and other platforms Presentation |
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[Will12a] S. Willenbrock Speculative Execution of Data Flow Process Networks Master Thesis |
2011
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[Blat11] D. Blatner Out-of-Order Execution of Data-flow Process Networks for Streaming Applications Bachelor Thesis |
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[GTBS11] G. Gaydadjiev and S. Tahar and G. Byrd and K. Schneider International Conference on Computer Design (ICCD) |
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[Kolt11] D. Koltermann Vektorisierungstechniken zur Nutzung der Multimedia-Extensions |
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[Kolt11a] D. Koltermann Vektorisierungstechniken zur Nutzung der Multimedia-Extensions Presentation |
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[Nazi11] R. Nazier Parallel Programming Models and Hybrid MPI/SMPSs Approach |
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[Nazi11a] R. Nazier Parallel Programming Models and Hybrid MPI/SMPSs Approach Presentation |
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[Senf11] M. Senftleben Web-based instruction-level simulation of a parameterized dynamic processor Bachelor Thesis |
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[Thul11] J. Thull Translating OpenMP Programs for Distributed-Memory Systems |
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[Thul11a] J. Thull Translating OpenMP Programs for Distributed-Memory Systems Presentation |
2010
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[BELS10] A. Benveniste and S.A. Edwards and E. Lee and K. Schneider and R. von Hanxleden SYNCHRON: Abstracts Collection of Dagstuhl Seminar 09481 |
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[Bai10] Y. Bai Dependency Analysis of Synchronous Programming Languages Master Thesis |
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[GeBS10] M. Gemünde and J. Brandt and K. Schneider Clock Refinement in Imperative Synchronous Languages SYNCHRON'09: Abstracts Collection of Dagstuhl Seminar 09481 |
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[Morg10] A. Morgenstern Symbolic Controller Synthesis for LTL Specifications PhD Thesis |
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[Rope10] T. Ropertz Efficient Execution of Synchronous Guarded Actions using CUDA Bachelor Thesis |
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[SJCB10] K. Schneider and B. Jobstmann and L. Carloni and J. Brandt Formal Methods and Models for Codesign (MEMOCODE) |
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[Will10] A. Willenbücher Optimizing Combinational Circuits for FPGAs Using Genetic Programming Master Thesis |
2008
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[Baud08] D. Baudisch Synthesis for VLIW Architectures Diploma Thesis |
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[Baue08b] K. Bauer Algebraic Methods and Abstractions for Automated 3-valued Reasoning on Hybrid Automata Diploma Thesis |
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[DyWi08] S. Dyckmans and A. Willenbücher Design and Implementation of a Dataflow-Processor for Synchronous Programs Bachelor Thesis |
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[EdSc08] S. Edwards and K. Schneider Formal Methods and Models for Codesign (MEMOCODE) |
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[Gemu08] M. Gemünde Evaluation Environment for AUTOSAR-Autocode in Motor Control Units Diploma Thesis |
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[Gese08] M. Gesell Probabilistic Model Checking of Synchronous Programs Diploma Thesis |
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[Schm08] S. Schmitt Supervisor Synthesis using SAT-Solvers Diploma Thesis |
2007
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[Baue07] K. Bauer On the Use of Gröbner Bases and Algebraic Methods for the Analysis of Hybrid Automata Project Thesis |
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[Baue07a] K. Bauer Three-valued $\mu$-Calculus on Hybrid Automata Diploma Thesis |
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[Bran07] J. Brandt A Layered Approach to Polygon Processing for Safety-Critical Embedded Systems PhD Thesis |
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[GeGe07] M. Gesell and M. Gemünde Eine Oberfläche zur Simulation synchroner Sprachen Project Thesis |
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[HoSc07] J.C. Hoe and K. Schneider Formal Methods and Models for Codesign (MEMOCODE) |
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[ScBr07] K. Schneider and J. Brandt Theorem Proving in Higher Order Logics (TPHOL) |
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[Schu07] T. Schüle Verification of Infinite State Systems Using Presburger Arithmetic PhD Thesis |
2006
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[Baud06] D. Baudisch Implementierung und Verifikation eines RISC-Prozessors in Averest Project Thesis |
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[BrSc06] J. Brandt and K. Schneider Multimedia-Hardwareerweiterungen |
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[Frie06] M. Friedrich Design and Implementation of a FCC Schedule Planner for an unmanned aircraft demonstrator Diploma Thesis |
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[Wagn06] C. Wagner Automatenbasierte Entscheidungsverfahren für Presburger-Arithmetik Diploma Thesis |
2005
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[Cron05] B. Cronauer XML-basierte Konfiguration von Steuergeräten Diploma Thesis |
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[Schm05] M. Schmidt An Algorithm for Restriction of Finite Automata Diploma Thesis |
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[Tuer05] T. Türk A Hierarchy for Accellera's Property Specification Language Diploma Thesis |
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[Wagn05a] C. Wagner Evaluierung von Algorithmen zur Berechnung fairer Pfade Project Thesis |
2004
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[Cron04] B. Cronauer Entwicklung eines embedded SPFH-Signal-Simulators für das John Deere GreenStar Office System |
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[Gent04] R. Gentilini Graph Algorithms for Massive Data-Sets PhD Thesis |
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[Ober04] A. Obermann Verifikation kryptographischer Protokolle mit Baumtransduktoren Diploma Thesis |
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[Webe04] J. Weber Entwurf eines RISC Prozessors mit synchronen Sprachen Diploma Thesis |
2003
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[Bran03] J. Brandt 2D-Polygon-Clipping Algorithmen für eingebettete Echtzeitsysteme Diploma Thesis |
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[Metz03] C. Metzler WCET-Analyse mit symbolischen Verfahren Diploma Thesis |
2001
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[Muel01] A. Müller Entwurf und Realisierung eines eingebetteten Systems zur Steuerung eines automatisierten Kalibrierkanals für Strömungssonden Project Thesis |
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[Wenz01] M. Wenz Codeerzeugung für die synchrone Modellierungssprache Quartz Diploma Thesis |
1999
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[Stit99] P. Stitzelberger übersetzung von VHDL-Strukturbeschreibungen in die synchrone Beschreibungssprache PURR Diploma Thesis |
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[Zimm99] J. Zimmermann Implementierung eines Entwurfs-und Verifikationswerkzeuges für die synchrone Programmiersprache PURR Master Thesis |
1998
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[Schr98] J. Schröder-Babo Anwendung spezieller Modellprüfungstechniken bei der Verifikation einer mehrfähdigen Prozessorarchitektur Project Thesis |
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[Zimm98] J. Zimmermann Verifikation der diskreten Cosinus-Transformation mittels Modellprüfung Project Thesis |
1997
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[Kuec97] G. Küçük Eine synchrone generische Hardwarebeschreibungssprache für die Verifikation mit induktiven Verfahren sowie Modellierung temporaler Logik Diploma Thesis |
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[Wein97] H. Weindel Verifikation von Zeitbedingungen mittels arithmetischer Entscheidungsverfahren Diploma Thesis |
1996
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[Amor96] M.G. Ben Amor Implementierung eines Modellprüfers für die verzweigende temporale Logik CTL* Diploma Thesis |
1995
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[Garb95] R.-U. Garbe Implementierung eines hierarchischen Verifikationsverfahrens mit $\omega$-Automaten Project Thesis |
1993
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[Eise93] D. Eisenbiegler Ein funktionaler Ansatz zur systematischen Formalisierung regulärer Schaltungen Diploma Thesis |