Search Result
2024
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[Desh24] S. Deshmukh Scenario Based Software Testing for Autonomous Truck Master Thesis |
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[Fass24] A. Faßbender Empirische Evaluierung der Effekte von Hardwarebeschleunigung auf quantenresistente Kryptographie im TLS 1.3 Protokoll Bachelor Thesis |
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[Hemm24b] L. Hemmerling Evaluierung der Verkettung von Recheneinheiten in exponierten Datenflussarchitekturen Bachelor Thesis |
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[Jose24] A.P. Jose A Microkernel based solution for SAFE Deadline Monitoring Master Thesis |
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[Moze24] D. Mozek Evaluating the Potential of Hardware-Acceleration for WebAssembly Bachelor Thesis |
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[Saji24] K.B. Sajikumar Modeling Hazardous Events in Automated Driving for Probabilistic Approach of Test Instrumentation Master Thesis |
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[Schr24] E. Schreiner BDD Minimization Through FSM State Re-Encoding Master Thesis |
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[Siva24] A. Sivaprasad Automated Model and Scenario Setup to Derive Functional Safety Criteria Master Thesis |
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[Sunn24] A. Sunny Conception and Implementation of a Test Control System for Complex Driving Scenarios for Driver Assistance Functions in Commercial Vehicles Master Thesis |
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[Tego24] F. Tego Efficient Translation of Linear Temporal Logic to Deterministic Automata Master Thesis |
2023
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[Bort23] E. Borth Generating parallel OpenCL and OpenMP Programs from Dataflow Graphs Bachelor Thesis |
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[Diet23a] F. Dietrich Tail Duplication for Compilation for Buffered Exposed Datapath Architectures Bachelor Thesis |
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[Ejla23] N. Ejlali Representing threat models by the Open Security Controls Assessment Language (OSCAL) Master Thesis |
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[Frei23] J. Freiermuth Echtzeit-Schaltassistent fü̈r Elektrofahrzeuge mit Schaltgetriebe Master Thesis |
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[Gupt23] A. Gupta A Model Driven Migration of Complex Legacy Solutions to a new ABAP software stack Master Thesis |
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[Haeu23] M. Häuser Designing a Secure and Space-Efficient Executable File Format for the Unified Extensible Firmware Interface Master Thesis |
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[Kerc23] N. Kercher Code Generation for Buffered Exposed Datapath Architectures Master Thesis |
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[Kozi23] S. Koziakov Towards a safe user-level virtual machine monitor for L4Re Master Thesis |
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[Neuh23] Y. Neuhard Developing an Augmented Reality Solution with GPU/CUDA Support to Evaluate and Visualize V2X Scenarios in a Driving Vehicle Master Thesis |
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[Wern23] L. Werner Performance Evaluation of Interconnection Networks on Processors Bachelor Thesis |
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[Zeun23] J. Zeunert Assessing the Security of Integrating SystemVerilog Synthesis and Simulation in Untrusted Environments Master Thesis |
2022
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[Balk22] D. Balke Consistency and Robustness in an Event-sourced System Bachelor Thesis |
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[Luet22] A.D. Lütke-Bordewick Instruction Scheduling for Exposed Datapath Architectures Bachelor Thesis |
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[Mahm22] H.M.A. Mahmoud Mapping Dataflow Process Networks on Real-time Operating Systems Bachelor Thesis |
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[Nara22] S.S. Naragund Sequencing Constraints in Contract-based verification Master Thesis |
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[Nara22a] A. Narasimhan Evaluation of Binary Moment Diagrams Master Thesis |
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[Rame22] R. Ramesh Decompilation of Move Programs to Dataflow Process Networks Master Thesis |
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[Thei22] D. Theis Symbolic Execution of Synchronous Quartz Programs Master Thesis |
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[Upad22] S. Upadhye Data-Driven System Design Based on the Development Data Master Thesis |
2021
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[Dahl21] M. Dahlem Using Enhanced Logic Programming Semantics for Extending and Optimizing Synchronous System Design PhD Thesis |
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[Feth21] M.T. Feth A Resource-Constrained Implementation of an Educational Microprocessor Bachelor Thesis |
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[Goka21] G. Gokaj Analysis of a Tableau-based Decision Procedure for CTL* Bachelor Thesis |
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[Rafi21] O. Rafique Embedded Software Synthesis using Heterogeneous Dataflow Models PhD Thesis |
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[Sale21] A. Saleem Steuerwerkssynthese für Datenflussprogramme Bachelor Thesis |
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[Schn21c] A. Schneiders A Comparison of Exposed Datapath and Conventional Processor Architectures Master Thesis |
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[Stei21] M. Stein Optimizing Overhead in Compilation for SCAD Architectures Master Thesis |
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[Stoc21] J. Stock Konfigurationsmanagement mit fachlichen Nutzern als Zielgruppe für ein technisch komplexes System Bachelor Thesis |
2020
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[Bhag20] A. Bhagyanath Code Generation for Synchronous Control Asynchronous Dataflow Architectures PhD Thesis |
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[Drew20] M. Drewniok Programmtransformation zur Vereinfachung des Kontrollflusses Bachelor Thesis |
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[Haid20] S.M. Haider Evaluating Scheduling Strategies for Executing Neural Networks on OpenCL Platforms Master Thesis |
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[Lill20] M. Lill Comparing SSA Code Transformations in Compilers Bachelor Thesis |
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[Rama20] P.K. Ramachandran Verification of SysML Models using Hybrid-Testbeds with Model-in-the-Loop Simulations Master Thesis |
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[Subr20] S.N. Subramanya An Evaluation of WebAssembly on Edge Devices for IoT Master Thesis |
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[Tiss20] S. Tissen Entwicklung eines Machine-Learning Modells zur Auswertung von Überlebensdaten und Bereitstellung als Web-Service Bachelor Thesis |
2019
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[AnKL19] M. Anders and S. Kwasigroch and M. Lederer Applied Verification Tasks Project Thesis |
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[Desh19] P.D. Deshmukh Verification of AUTOSAR Basis Software Master Thesis |
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[Haid19] S.M. Haider Synthesis Framework for Executing Neural Networks on Heterogeneous Platforms Master Thesis |
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[Harc19] A. Harchandani How to Refine Support Experience Using Machine Learning Master Thesis |
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[Hass19] F. Hasselwander Lemma Generation for Induction-based Proof Rules Master Thesis |
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[Jain19] T. Jain Nonblocking On-Chip Interconnection Networks PhD Thesis |
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[Kreb19] F. Krebs A Translation Framework from RVC-CAL Dataflow Programs to OpenCL/SYCL based Implementations Master Thesis |
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[Lede19] M. Lederer Causal Correctness as a Safety Property Bachelor Thesis |
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[Moha19] M. Mohamed SIMULINK to DLL (for TSIM Plugin) Project Thesis |
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[Mukh19] P.S. Mukherjee Data-driven Control with Machine Learning for Optimization of a Cement Mill Master Thesis |
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[Senf19] M. Senftleben Modelling Memory Consistency Models for Formal Verification PhD Thesis |
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[Thei19] D. Theis Restrukturierung der API und Serverkomponente eines mobilen Spiels zur Optimierung der Sicherheit Bachelor Thesis |
2018
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[Ande18] M. Anders Foundations for Verifiable Reactive Systems on Exposed Datapath Architectures with Buffered Processing Units Project Thesis |
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[Bhat18] S.N. Bhat Robustness Assessment of Linux by Simulation-Based Physical Fault Injection in System Calls Master Thesis |
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[Bonk18] J. Bonkile Development Tools Tailored for Serverless Cloud Computing Master Thesis |
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[Buss18] L. Busser Evaluating Learning Algorithms for Regular Expressions Bachelor Thesis |
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[Das18a] T. Das Classification of Warranty Claim Data using Supervised Machine Learning Algorithm SVM (Support Vector Machine) Master Thesis |
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[Dsou18] E.A. Dsouza Optical Communication in High Voltage Battery Systems Master Thesis |
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[Geor18] G. Georgopoulos Operational Semantics of Memory System Implementations Master Thesis |
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[Schn18] A. Schneiders Using Static-Single-Information-Form for SCAD Code Generation Bachelor Thesis |
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[Schu18] S. Schumb Evaluating Interconnection Networks for Exposed Datapath Architectures Master Thesis |
2017
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[Ande17] M. Anders Complexity Analysis of Code Generation for the SCAD Machine Bachelor Thesis |
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[Basa17] S.R. Basavaraju Application-specific Configuration of Exposed Datapath Architectures Master Thesis |
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[Haif17] F. Haifani Antichain Optimization using Simulation Relations for Context-Free Games Master Thesis |
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[Kann17] S. Kannoth Synchronous Modelling and Formal Verification of Train Command Management Systems Master Thesis |
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[Li17] X. Li Induction-based Verification of Synchronous and Hybrid Programs PhD Thesis |
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[Neum17] E. Neumann Algorithms for Context-free Games: A Comparison of Saturation, Guess and Check, and Summarization Master Thesis |
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[Roob17] J. Roob OpenCL Implementation of Exposed Data Path Architectures as General Purpose Accelerators Master Thesis |
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[Stat17] M. Stather Entwicklung einer Kommunikationskomponente mit Sensor-/Aktorinterface auf einem FPGA für das Finroc-Projekt Bachelor Thesis |
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[Stut17] F.M. Stutz Operations on a Symbolic Domain for Synthesis Bachelor Thesis |
2016
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[Bai16] Y. Bai Model-based Design of Embedded Systems by Desynchronization PhD Thesis |
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[Dein16] D. Deiniger Application of Factored Representations from Probabilistic Graphical Models to Probabilistic Verification Master Thesis |
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[Harm16] C. Harms Evaluation of FPGA-based Implementations of Interconnection Networks Master Thesis |
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[Heer16] M. Heer Verification Condition Generation for Hybrid Systems described by Synchronous Languages Master Thesis |
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[John16] M.R. John Static Instruction Scheduling for Transport Triggered Architectures Master Thesis |
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[Kabo16] A. Kabouteh Formal Method Based Analysis of an Ophthalmic Surgical Robot Considering Hard Real-Time Constraints Master Thesis |
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[Rao16] A. Rao Implementation of a Software Emulator to recreate I2C Sensor Communication Master Thesis |
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[Walk16a] F. Walk Out-of-Order Execution Within Functional Units of the SCAD Architecture Master Thesis |
2015
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[Ashr15] K. Ashraf HW/SW Co-design and Implementation of a Fountain Code for an FPGA System-on-Chip Master Thesis |
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[Bich15] F. Bichued Verification of Microprocessors Master Thesis |
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[Blat15] D. Blatner Automatisierte Transformationen von Petri-Netzen zur detaillierten Ablaufkontrolle in verteilten Laufzeitsystemen Master Thesis |
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[Garc15] H. Lázaro García Using UVM for Mixed-Signal Verification with IGBT Driver Context Master Thesis |
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[Schu15] S. Schumb Hardware Generation for Transport Triggered Architectures Bachelor Thesis |
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[Shaz15] T. Shazadi Evaluation of Dataflow Process Networks Mapping on Multi-core Processors Master Thesis |
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[Stra15] J. Stratmann Implementation and Verification of IEEE-conform Floating-Point Arithmetic Master Thesis |
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[Tria15] A. Triambak Dynamic Scheduling of Instructions in Transport Triggered Architecture based Processors Master Thesis |
2014
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[Dahl14] M. Dahlem Interactive Verification of Synchronous Systems in HOL Master Thesis |
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[Gese14] M. Gesell Interactive Verification of Synchronous Systems PhD Thesis |
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[Heer14] M. Heer Assembler Code-Generierung aus synchronen Aktionen Bachelor Thesis |
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[Maca14] M.N. Basurto Macavilca Endochrony of Distributed Systems Diploma Thesis |
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[Rede14] M. Reder Code Generation for Transport Triggered Architecture Bachelor Thesis |
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[Rome14] A. Gerlinger Romero Hybrid fUML: A Hybrid Synchronous Language PhD Thesis |
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[Roob14] J. Roob A Hardware Abstraction Layer for Model-based Design of Embedded Systems Bachelor Thesis |
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[Thie14] D. Thielsch Analysis of Concurrency in Synchronous Systems Master Thesis |
2013
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[Baud13] D. Baudisch Synthesis of Synchronous Programs to Parallel Software Architectures PhD Thesis |
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[Bran13] J. Brandt Synchronous Models for Embedded Software Habilitation Thesis |
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[Gemu13a] M. Gemünde Clock Refinement in Imperative Synchronous Programs PhD Thesis |
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[Humb13] Y. Humbert Umsetzung und Vergleich der Ausführung einer rechenintensiven Echtzeitanwendung mittels OpenMP und CUDA am Beispiel des Beamforming-Algorithmus Master Thesis |
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[Khad13] M.A. Ben Khadra A Model-based Approach To Sychronous Elastic Systems Master Thesis |
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[Rafi13] O. Rafique Design, Development, and Integration of a Wireless Communication Unit in ConceptCar Master Thesis |
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[Senf13] M. Senftleben Operational Characterization of Weak Memory Consistency Models Master Thesis |
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[Walk13] F. Walk Parallel Software Generated from Synchronous Programs -- A Performance Evaluation Using a Ray Tracer Bachelor Thesis |
2012
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[Baue12] K. Bauer A New Modelling Language for Cyber-physical Systems PhD Thesis |
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[Eick12] T. Eickhoff Program Sketching Using Craig Interpolants Bachelor Thesis |
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[Liet12] B. Lietzow A Domain Specific Language for the Synthesis of Networked Embedded Systems Master Thesis |
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[Stra12] J. Stratmann Design and Implementation of a Floating-Point Application Specific Instruction Set Processor Bachelor Thesis |
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[Thie12] D. Thielsch Criteria of Endo/Isochrony in Quartz Bachelor Thesis |
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[Thul12] J. Thull Ein Testkonzept für Efficient XML Interchange (EXI) im Automobilbereich Master Thesis |
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[Will12a] S. Willenbrock Speculative Execution of Data Flow Process Networks Master Thesis |
2011
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[Blat11] D. Blatner Out-of-Order Execution of Data-flow Process Networks for Streaming Applications Bachelor Thesis |
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[Senf11] M. Senftleben Web-based instruction-level simulation of a parameterized dynamic processor Bachelor Thesis |
2010
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[Bai10] Y. Bai Dependency Analysis of Synchronous Programming Languages Master Thesis |
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[Morg10] A. Morgenstern Symbolic Controller Synthesis for LTL Specifications PhD Thesis |
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[Rope10] T. Ropertz Efficient Execution of Synchronous Guarded Actions using CUDA Bachelor Thesis |
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[Will10] A. Willenbücher Optimizing Combinational Circuits for FPGAs Using Genetic Programming Master Thesis |
2008
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[Baud08] D. Baudisch Synthesis for VLIW Architectures Diploma Thesis |
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[Baue08b] K. Bauer Algebraic Methods and Abstractions for Automated 3-valued Reasoning on Hybrid Automata Diploma Thesis |
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[DyWi08] S. Dyckmans and A. Willenbücher Design and Implementation of a Dataflow-Processor for Synchronous Programs Bachelor Thesis |
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[Gemu08] M. Gemünde Evaluation Environment for AUTOSAR-Autocode in Motor Control Units Diploma Thesis |
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[Gese08] M. Gesell Probabilistic Model Checking of Synchronous Programs Diploma Thesis |
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[Schm08] S. Schmitt Supervisor Synthesis using SAT-Solvers Diploma Thesis |
2007
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[Baue07] K. Bauer On the Use of Gröbner Bases and Algebraic Methods for the Analysis of Hybrid Automata Project Thesis |
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[Baue07a] K. Bauer Three-valued $\mu$-Calculus on Hybrid Automata Diploma Thesis |
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[Bran07] J. Brandt A Layered Approach to Polygon Processing for Safety-Critical Embedded Systems PhD Thesis |
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[GeGe07] M. Gesell and M. Gemünde Eine Oberfläche zur Simulation synchroner Sprachen Project Thesis |
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[Schu07] T. Schüle Verification of Infinite State Systems Using Presburger Arithmetic PhD Thesis |
2006
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[Baud06] D. Baudisch Implementierung und Verifikation eines RISC-Prozessors in Averest Project Thesis |
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[Frie06] M. Friedrich Design and Implementation of a FCC Schedule Planner for an unmanned aircraft demonstrator Diploma Thesis |
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[Wagn06] C. Wagner Automatenbasierte Entscheidungsverfahren für Presburger-Arithmetik Diploma Thesis |
2005
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[Cron05] B. Cronauer XML-basierte Konfiguration von Steuergeräten Diploma Thesis |
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[Schm05] M. Schmidt An Algorithm for Restriction of Finite Automata Diploma Thesis |
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[Tuer05] T. Türk A Hierarchy for Accellera's Property Specification Language Diploma Thesis |
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[Wagn05a] C. Wagner Evaluierung von Algorithmen zur Berechnung fairer Pfade Project Thesis |
2004
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[Gent04] R. Gentilini Graph Algorithms for Massive Data-Sets PhD Thesis |
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[Ober04] A. Obermann Verifikation kryptographischer Protokolle mit Baumtransduktoren Diploma Thesis |
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[Webe04] J. Weber Entwurf eines RISC Prozessors mit synchronen Sprachen Diploma Thesis |
2003
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[Bran03] J. Brandt 2D-Polygon-Clipping Algorithmen für eingebettete Echtzeitsysteme Diploma Thesis |
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[Metz03] C. Metzler WCET-Analyse mit symbolischen Verfahren Diploma Thesis |
2001
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[Muel01] A. Müller Entwurf und Realisierung eines eingebetteten Systems zur Steuerung eines automatisierten Kalibrierkanals für Strömungssonden Project Thesis |
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[Wenz01] M. Wenz Codeerzeugung für die synchrone Modellierungssprache Quartz Diploma Thesis |
1999
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[Stit99] P. Stitzelberger übersetzung von VHDL-Strukturbeschreibungen in die synchrone Beschreibungssprache PURR Diploma Thesis |
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[Zimm99] J. Zimmermann Implementierung eines Entwurfs-und Verifikationswerkzeuges für die synchrone Programmiersprache PURR Master Thesis |
1998
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[Schr98] J. Schröder-Babo Anwendung spezieller Modellprüfungstechniken bei der Verifikation einer mehrfähdigen Prozessorarchitektur Project Thesis |
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[Zimm98] J. Zimmermann Verifikation der diskreten Cosinus-Transformation mittels Modellprüfung Project Thesis |
1997
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[Kuec97] G. Küçük Eine synchrone generische Hardwarebeschreibungssprache für die Verifikation mit induktiven Verfahren sowie Modellierung temporaler Logik Diploma Thesis |
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[Wein97] H. Weindel Verifikation von Zeitbedingungen mittels arithmetischer Entscheidungsverfahren Diploma Thesis |
1996
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[Amor96] M.G. Ben Amor Implementierung eines Modellprüfers für die verzweigende temporale Logik CTL* Diploma Thesis |
1995
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[Garb95] R.-U. Garbe Implementierung eines hierarchischen Verifikationsverfahrens mit $\omega$-Automaten Project Thesis |
1993
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[Eise93] D. Eisenbiegler Ein funktionaler Ansatz zur systematischen Formalisierung regulärer Schaltungen Diploma Thesis |