Discrete Event Based Systems

Discrete event based languages have been developed for fast simulation [CaLa08]. Many hardware description languages like VHDL, Verilog, SystemC, and SystemVerilog, but also others like Simulink are based on this language paradigm. The main idea is thereby that the system considered consists of a finite number of processes where the code of each process contains special wait-statements that are associated with an event they are awaiting for. This event may be the arrival of a certain point of time, the change of a variable, or the satisfaction of a boolean expression. A special simulation process elaborates the code of the processes of the system from their current wait statements until the next wait-statements are reached. Elaborating means that the right hand sides of assignments are evaluated but instead of assigning the obtained values, an entry for a schedule is generated that makes this assignment later on. After the elaboration, the next point of time is determined by inspecting the schedule. Then the actions associated with that point of time are committed, which leads to a set of events. This set of events activates some of the processes that are elaborated next.

Obviously, discrete event based languages are perfectly suited for simulators that run on sequential machines since only processes are elaborated that are activated by generated events. Languages like VHDL and Verilog are however also used for hardware synthesis, where typically the set of events is reduced to clock events, and in this sense, one essentially writes a clock-based system in an event-based language.

References

			[CaLa08] C.G. Cassandras and S. Lafortune Introduction to Discrete Event Systems Springer
			[IEEE08] IEEE IEEE Standard VHDL Language Reference Manual
			[IEEE05] IEEE IEEE Standard SystemC Language Reference Manual
			[IEEE96] IEEE IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language